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ff772b27e5
Using vendor-provided magic, add code to enter power save mode on the PHY. We'll need this for suspend and wake-on-lan. Signed-off-by: Jay Cliburn <jacliburn@bellsouth.net> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
509 lines
18 KiB
C
509 lines
18 KiB
C
/* atlx_hw.h -- common hardware definitions for Attansic network drivers
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*
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* Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
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* Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
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* Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
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* Copyright(c) 2007 Atheros Corporation. All rights reserved.
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*
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* Derived from Intel e1000 driver
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* Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59
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* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef ATLX_H
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#define ATLX_H
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#include <linux/module.h>
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#include <linux/types.h>
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#define ATLX_DRIVER_VERSION "2.1.1"
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MODULE_AUTHOR("Xiong Huang <xiong.huang@atheros.com>, \
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Chris Snook <csnook@redhat.com>, Jay Cliburn <jcliburn@gmail.com>");
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MODULE_LICENSE("GPL");
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MODULE_VERSION(ATLX_DRIVER_VERSION);
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#define ATLX_ERR_PHY 2
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#define ATLX_ERR_PHY_SPEED 7
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#define ATLX_ERR_PHY_RES 8
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#define SPEED_0 0xffff
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#define SPEED_10 10
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#define SPEED_100 100
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#define SPEED_1000 1000
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#define HALF_DUPLEX 1
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#define FULL_DUPLEX 2
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#define MEDIA_TYPE_AUTO_SENSOR 0
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/* register definitions */
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#define REG_PM_CTRLSTAT 0x44
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#define REG_PCIE_CAP_LIST 0x58
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#define REG_VPD_CAP 0x6C
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#define VPD_CAP_ID_MASK 0xFF
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#define VPD_CAP_ID_SHIFT 0
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#define VPD_CAP_NEXT_PTR_MASK 0xFF
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#define VPD_CAP_NEXT_PTR_SHIFT 8
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#define VPD_CAP_VPD_ADDR_MASK 0x7FFF
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#define VPD_CAP_VPD_ADDR_SHIFT 16
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#define VPD_CAP_VPD_FLAG 0x80000000
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#define REG_VPD_DATA 0x70
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#define REG_SPI_FLASH_CTRL 0x200
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#define SPI_FLASH_CTRL_STS_NON_RDY 0x1
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#define SPI_FLASH_CTRL_STS_WEN 0x2
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#define SPI_FLASH_CTRL_STS_WPEN 0x80
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#define SPI_FLASH_CTRL_DEV_STS_MASK 0xFF
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#define SPI_FLASH_CTRL_DEV_STS_SHIFT 0
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#define SPI_FLASH_CTRL_INS_MASK 0x7
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#define SPI_FLASH_CTRL_INS_SHIFT 8
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#define SPI_FLASH_CTRL_START 0x800
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#define SPI_FLASH_CTRL_EN_VPD 0x2000
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#define SPI_FLASH_CTRL_LDSTART 0x8000
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#define SPI_FLASH_CTRL_CS_HI_MASK 0x3
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#define SPI_FLASH_CTRL_CS_HI_SHIFT 16
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#define SPI_FLASH_CTRL_CS_HOLD_MASK 0x3
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#define SPI_FLASH_CTRL_CS_HOLD_SHIFT 18
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#define SPI_FLASH_CTRL_CLK_LO_MASK 0x3
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#define SPI_FLASH_CTRL_CLK_LO_SHIFT 20
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#define SPI_FLASH_CTRL_CLK_HI_MASK 0x3
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#define SPI_FLASH_CTRL_CLK_HI_SHIFT 22
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#define SPI_FLASH_CTRL_CS_SETUP_MASK 0x3
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#define SPI_FLASH_CTRL_CS_SETUP_SHIFT 24
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#define SPI_FLASH_CTRL_EROM_PGSZ_MASK 0x3
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#define SPI_FLASH_CTRL_EROM_PGSZ_SHIFT 26
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#define SPI_FLASH_CTRL_WAIT_READY 0x10000000
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#define REG_SPI_ADDR 0x204
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#define REG_SPI_DATA 0x208
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#define REG_SPI_FLASH_CONFIG 0x20C
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#define SPI_FLASH_CONFIG_LD_ADDR_MASK 0xFFFFFF
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#define SPI_FLASH_CONFIG_LD_ADDR_SHIFT 0
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#define SPI_FLASH_CONFIG_VPD_ADDR_MASK 0x3
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#define SPI_FLASH_CONFIG_VPD_ADDR_SHIFT 24
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#define SPI_FLASH_CONFIG_LD_EXIST 0x4000000
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#define REG_SPI_FLASH_OP_PROGRAM 0x210
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#define REG_SPI_FLASH_OP_SC_ERASE 0x211
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#define REG_SPI_FLASH_OP_CHIP_ERASE 0x212
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#define REG_SPI_FLASH_OP_RDID 0x213
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#define REG_SPI_FLASH_OP_WREN 0x214
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#define REG_SPI_FLASH_OP_RDSR 0x215
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#define REG_SPI_FLASH_OP_WRSR 0x216
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#define REG_SPI_FLASH_OP_READ 0x217
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#define REG_TWSI_CTRL 0x218
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#define TWSI_CTRL_LD_OFFSET_MASK 0xFF
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#define TWSI_CTRL_LD_OFFSET_SHIFT 0
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#define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7
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#define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8
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#define TWSI_CTRL_SW_LDSTART 0x800
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#define TWSI_CTRL_HW_LDSTART 0x1000
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#define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x7F
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#define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15
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#define TWSI_CTRL_LD_EXIST 0x400000
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#define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3
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#define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23
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#define TWSI_CTRL_FREQ_SEL_100K 0
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#define TWSI_CTRL_FREQ_SEL_200K 1
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#define TWSI_CTRL_FREQ_SEL_300K 2
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#define TWSI_CTRL_FREQ_SEL_400K 3
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#define TWSI_CTRL_SMB_SLV_ADDR /* FIXME: define or remove */
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#define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3
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#define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24
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#define REG_PCIE_DEV_MISC_CTRL 0x21C
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#define PCIE_DEV_MISC_CTRL_EXT_PIPE 0x2
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#define PCIE_DEV_MISC_CTRL_RETRY_BUFDIS 0x1
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#define PCIE_DEV_MISC_CTRL_SPIROM_EXIST 0x4
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#define PCIE_DEV_MISC_CTRL_SERDES_ENDIAN 0x8
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#define PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN 0x10
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#define REG_PCIE_PHYMISC 0x1000
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#define PCIE_PHYMISC_FORCE_RCV_DET 0x4
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#define REG_PCIE_DLL_TX_CTRL1 0x1104
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#define PCIE_DLL_TX_CTRL1_SEL_NOR_CLK 0x400
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#define PCIE_DLL_TX_CTRL1_DEF 0x568
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#define REG_LTSSM_TEST_MODE 0x12FC
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#define LTSSM_TEST_MODE_DEF 0x6500
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/* Master Control Register */
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#define REG_MASTER_CTRL 0x1400
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#define MASTER_CTRL_SOFT_RST 0x1
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#define MASTER_CTRL_MTIMER_EN 0x2
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#define MASTER_CTRL_ITIMER_EN 0x4
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#define MASTER_CTRL_MANUAL_INT 0x8
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#define MASTER_CTRL_REV_NUM_SHIFT 16
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#define MASTER_CTRL_REV_NUM_MASK 0xFF
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#define MASTER_CTRL_DEV_ID_SHIFT 24
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#define MASTER_CTRL_DEV_ID_MASK 0xFF
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/* Timer Initial Value Register */
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#define REG_MANUAL_TIMER_INIT 0x1404
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/* IRQ Moderator Timer Initial Value Register */
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#define REG_IRQ_MODU_TIMER_INIT 0x1408
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#define REG_PHY_ENABLE 0x140C
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/* IRQ Anti-Lost Timer Initial Value Register */
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#define REG_CMBDISDMA_TIMER 0x140E
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/* Block IDLE Status Register */
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#define REG_IDLE_STATUS 0x1410
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/* MDIO Control Register */
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#define REG_MDIO_CTRL 0x1414
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#define MDIO_DATA_MASK 0xFFFF
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#define MDIO_DATA_SHIFT 0
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#define MDIO_REG_ADDR_MASK 0x1F
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#define MDIO_REG_ADDR_SHIFT 16
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#define MDIO_RW 0x200000
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#define MDIO_SUP_PREAMBLE 0x400000
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#define MDIO_START 0x800000
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#define MDIO_CLK_SEL_SHIFT 24
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#define MDIO_CLK_25_4 0
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#define MDIO_CLK_25_6 2
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#define MDIO_CLK_25_8 3
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#define MDIO_CLK_25_10 4
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#define MDIO_CLK_25_14 5
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#define MDIO_CLK_25_20 6
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#define MDIO_CLK_25_28 7
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#define MDIO_BUSY 0x8000000
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/* MII PHY Status Register */
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#define REG_PHY_STATUS 0x1418
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/* BIST Control and Status Register0 (for the Packet Memory) */
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#define REG_BIST0_CTRL 0x141C
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#define BIST0_NOW 0x1
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#define BIST0_SRAM_FAIL 0x2
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#define BIST0_FUSE_FLAG 0x4
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#define REG_BIST1_CTRL 0x1420
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#define BIST1_NOW 0x1
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#define BIST1_SRAM_FAIL 0x2
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#define BIST1_FUSE_FLAG 0x4
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/* SerDes Lock Detect Control and Status Register */
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#define REG_SERDES_LOCK 0x1424
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#define SERDES_LOCK_DETECT 1
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#define SERDES_LOCK_DETECT_EN 2
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/* MAC Control Register */
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#define REG_MAC_CTRL 0x1480
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#define MAC_CTRL_TX_EN 1
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#define MAC_CTRL_RX_EN 2
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#define MAC_CTRL_TX_FLOW 4
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#define MAC_CTRL_RX_FLOW 8
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#define MAC_CTRL_LOOPBACK 0x10
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#define MAC_CTRL_DUPLX 0x20
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#define MAC_CTRL_ADD_CRC 0x40
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#define MAC_CTRL_PAD 0x80
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#define MAC_CTRL_LENCHK 0x100
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#define MAC_CTRL_HUGE_EN 0x200
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#define MAC_CTRL_PRMLEN_SHIFT 10
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#define MAC_CTRL_PRMLEN_MASK 0xF
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#define MAC_CTRL_RMV_VLAN 0x4000
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#define MAC_CTRL_PROMIS_EN 0x8000
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#define MAC_CTRL_MC_ALL_EN 0x2000000
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#define MAC_CTRL_BC_EN 0x4000000
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/* MAC IPG/IFG Control Register */
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#define REG_MAC_IPG_IFG 0x1484
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#define MAC_IPG_IFG_IPGT_SHIFT 0
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#define MAC_IPG_IFG_IPGT_MASK 0x7F
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#define MAC_IPG_IFG_MIFG_SHIFT 8
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#define MAC_IPG_IFG_MIFG_MASK 0xFF
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#define MAC_IPG_IFG_IPGR1_SHIFT 16
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#define MAC_IPG_IFG_IPGR1_MASK 0x7F
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#define MAC_IPG_IFG_IPGR2_SHIFT 24
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#define MAC_IPG_IFG_IPGR2_MASK 0x7F
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/* MAC STATION ADDRESS */
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#define REG_MAC_STA_ADDR 0x1488
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/* Hash table for multicast address */
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#define REG_RX_HASH_TABLE 0x1490
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/* MAC Half-Duplex Control Register */
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#define REG_MAC_HALF_DUPLX_CTRL 0x1498
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#define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0
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#define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3FF
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#define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12
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#define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xF
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#define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000
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#define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000
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#define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000
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#define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000
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#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20
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#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xF
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#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24
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#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xF
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/* Maximum Frame Length Control Register */
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#define REG_MTU 0x149C
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/* Wake-On-Lan control register */
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#define REG_WOL_CTRL 0x14A0
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#define WOL_PATTERN_EN 0x1
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#define WOL_PATTERN_PME_EN 0x2
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#define WOL_MAGIC_EN 0x4
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#define WOL_MAGIC_PME_EN 0x8
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#define WOL_LINK_CHG_EN 0x10
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#define WOL_LINK_CHG_PME_EN 0x20
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#define WOL_PATTERN_ST 0x100
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#define WOL_MAGIC_ST 0x200
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#define WOL_LINKCHG_ST 0x400
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#define WOL_PT0_EN 0x10000
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#define WOL_PT1_EN 0x20000
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#define WOL_PT2_EN 0x40000
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#define WOL_PT3_EN 0x80000
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#define WOL_PT4_EN 0x100000
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#define WOL_PT0_MATCH 0x1000000
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#define WOL_PT1_MATCH 0x2000000
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#define WOL_PT2_MATCH 0x4000000
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#define WOL_PT3_MATCH 0x8000000
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#define WOL_PT4_MATCH 0x10000000
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/* Internal SRAM Partition Register, high 32 bits */
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#define REG_SRAM_RFD_ADDR 0x1500
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/* Descriptor Control register, high 32 bits */
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#define REG_DESC_BASE_ADDR_HI 0x1540
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/* Interrupt Status Register */
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#define REG_ISR 0x1600
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#define ISR_UR_DETECTED 0x1000000
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#define ISR_FERR_DETECTED 0x2000000
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#define ISR_NFERR_DETECTED 0x4000000
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#define ISR_CERR_DETECTED 0x8000000
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#define ISR_PHY_LINKDOWN 0x10000000
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#define ISR_DIS_INT 0x80000000
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/* Interrupt Mask Register */
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#define REG_IMR 0x1604
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#define REG_RFD_RRD_IDX 0x1800
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#define REG_TPD_IDX 0x1804
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/* MII definitions */
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/* PHY Common Register */
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#define MII_ATLX_CR 0x09
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#define MII_ATLX_SR 0x0A
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#define MII_ATLX_ESR 0x0F
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#define MII_ATLX_PSCR 0x10
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#define MII_ATLX_PSSR 0x11
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/* PHY Control Register */
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#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100,
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* 00=10
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*/
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#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
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#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
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#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
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#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
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#define MII_CR_POWER_DOWN 0x0800 /* Power down */
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#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
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#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100,
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* 00=10
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*/
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#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
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#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
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#define MII_CR_SPEED_MASK 0x2040
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#define MII_CR_SPEED_1000 0x0040
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#define MII_CR_SPEED_100 0x2000
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#define MII_CR_SPEED_10 0x0000
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/* PHY Status Register */
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#define MII_SR_EXTENDED_CAPS 0x0001 /* Ext register capabilities */
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#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
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#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
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#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
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#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
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#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
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#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
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#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext stat info in Reg 0x0F */
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#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
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#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
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#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
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#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
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#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
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#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
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#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
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/* Link partner ability register */
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#define MII_LPA_SLCT 0x001f /* Same as advertise selector */
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#define MII_LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
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#define MII_LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
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#define MII_LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
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#define MII_LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
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#define MII_LPA_100BASE4 0x0200 /* 100BASE-T4 */
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#define MII_LPA_PAUSE 0x0400 /* PAUSE */
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#define MII_LPA_ASYPAUSE 0x0800 /* Asymmetrical PAUSE */
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#define MII_LPA_RFAULT 0x2000 /* Link partner faulted */
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#define MII_LPA_LPACK 0x4000 /* Link partner acked us */
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#define MII_LPA_NPAGE 0x8000 /* Next page bit */
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/* Autoneg Advertisement Register */
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#define MII_AR_SELECTOR_FIELD 0x0001 /* IEEE 802.3 CSMA/CD */
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#define MII_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
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#define MII_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
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#define MII_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
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#define MII_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
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#define MII_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
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#define MII_AR_PAUSE 0x0400 /* Pause operation desired */
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#define MII_AR_ASM_DIR 0x0800 /* Asymmetric Pause Dir bit */
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#define MII_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
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#define MII_AR_NEXT_PAGE 0x8000 /* Next Page ability support */
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#define MII_AR_SPEED_MASK 0x01E0
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#define MII_AR_DEFAULT_CAP_MASK 0x0DE0
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/* 1000BASE-T Control Register */
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#define MII_ATLX_CR_1000T_HD_CAPS 0x0100 /* Adv 1000T HD cap */
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#define MII_ATLX_CR_1000T_FD_CAPS 0x0200 /* Adv 1000T FD cap */
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#define MII_ATLX_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device,
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* 0=DTE device */
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#define MII_ATLX_CR_1000T_MS_VALUE 0x0800 /* 1=Config PHY as Master,
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* 0=Configure PHY as Slave */
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#define MII_ATLX_CR_1000T_MS_ENABLE 0x1000 /* 1=Man Master/Slave config,
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* 0=Auto Master/Slave config
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*/
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#define MII_ATLX_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
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#define MII_ATLX_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
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#define MII_ATLX_CR_1000T_TEST_MODE_2 0x4000 /* Master Xmit Jitter test */
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#define MII_ATLX_CR_1000T_TEST_MODE_3 0x6000 /* Slave Xmit Jitter test */
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#define MII_ATLX_CR_1000T_TEST_MODE_4 0x8000 /* Xmitter Distortion test */
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#define MII_ATLX_CR_1000T_SPEED_MASK 0x0300
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#define MII_ATLX_CR_1000T_DEFAULT_CAP_MASK 0x0300
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/* 1000BASE-T Status Register */
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#define MII_ATLX_SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
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#define MII_ATLX_SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
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#define MII_ATLX_SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
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#define MII_ATLX_SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
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#define MII_ATLX_SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master
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* 0=Slave
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*/
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#define MII_ATLX_SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config
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* fault */
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#define MII_ATLX_SR_1000T_REMOTE_RX_STATUS_SHIFT 12
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#define MII_ATLX_SR_1000T_LOCAL_RX_STATUS_SHIFT 13
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/* Extended Status Register */
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#define MII_ATLX_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
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#define MII_ATLX_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
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#define MII_ATLX_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
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#define MII_ATLX_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
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/* ATLX PHY Specific Control Register */
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#define MII_ATLX_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Func disabled */
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#define MII_ATLX_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enbld */
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#define MII_ATLX_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
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#define MII_ATLX_PSCR_MAC_POWERDOWN 0x0008
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#define MII_ATLX_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low
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* 0=CLK125 toggling
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*/
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#define MII_ATLX_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5,
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* Manual MDI configuration
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*/
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#define MII_ATLX_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
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#define MII_ATLX_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover
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* 100BASE-TX/10BASE-T: MDI
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* Mode */
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#define MII_ATLX_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
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* all speeds.
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*/
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#define MII_ATLX_PSCR_10BT_EXT_DIST_ENABLE 0x0080 /* 1=Enable Extended
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* 10BASE-T distance
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* (Lower 10BASE-T RX
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* Threshold)
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* 0=Normal 10BASE-T RX
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* Threshold
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*/
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#define MII_ATLX_PSCR_MII_5BIT_ENABLE 0x0100 /* 1=5-Bit interface in
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* 100BASE-TX
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* 0=MII interface in
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* 100BASE-TX
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*/
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#define MII_ATLX_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler dsbl */
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#define MII_ATLX_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
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#define MII_ATLX_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
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#define MII_ATLX_PSCR_POLARITY_REVERSAL_SHIFT 1
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#define MII_ATLX_PSCR_AUTO_X_MODE_SHIFT 5
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#define MII_ATLX_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
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/* ATLX PHY Specific Status Register */
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#define MII_ATLX_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
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#define MII_ATLX_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
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#define MII_ATLX_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
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#define MII_ATLX_PSSR_10MBS 0x0000 /* 00=10Mbs */
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#define MII_ATLX_PSSR_100MBS 0x4000 /* 01=100Mbs */
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#define MII_ATLX_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
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#define MII_DBG_ADDR 0x1D
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#define MII_DBG_DATA 0x1E
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/* PCI Command Register Bit Definitions */
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#define PCI_REG_COMMAND 0x04 /* PCI Command Register */
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#define CMD_IO_SPACE 0x0001
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#define CMD_MEMORY_SPACE 0x0002
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#define CMD_BUS_MASTER 0x0004
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/* Wake Up Filter Control */
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#define ATLX_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
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#define ATLX_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
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#define ATLX_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
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#define ATLX_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */
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#define ATLX_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
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#define ADVERTISE_10_HALF 0x0001
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#define ADVERTISE_10_FULL 0x0002
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#define ADVERTISE_100_HALF 0x0004
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#define ADVERTISE_100_FULL 0x0008
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#define ADVERTISE_1000_HALF 0x0010
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#define ADVERTISE_1000_FULL 0x0020
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#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds */
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#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds */
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#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
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#define PHY_FORCE_TIME 20 /* 2.0 Seconds */
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/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA */
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#define EEPROM_SUM 0xBABA
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#define NODE_ADDRESS_SIZE 6
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struct atlx_spi_flash_dev {
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const char *manu_name; /* manufacturer id */
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/* op-code */
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u8 cmd_wrsr;
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u8 cmd_read;
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u8 cmd_program;
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u8 cmd_wren;
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u8 cmd_wrdi;
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u8 cmd_rdsr;
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u8 cmd_rdid;
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u8 cmd_sector_erase;
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u8 cmd_chip_erase;
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};
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#endif /* ATLX_H */
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