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4537f93ae8
The Display Control's CRT_EN can be shut off when we enter FB_BLANK_POWERDOWN in an attempt to save additional power. Signed-off-by: Andres Salomon <dilinger@debian.org> Cc: Jordan Crouse <jordan.crouse@amd.com> Cc: "Antonino A. Daplas" <adaplas@pol.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
349 lines
9.9 KiB
C
349 lines
9.9 KiB
C
/*
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* Geode GX video processor device.
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*
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* Copyright (C) 2006 Arcom Control Systems Ltd.
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*
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* Portions from AMD's original 2.4 driver:
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* Copyright (C) 2004 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/fb.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include <asm/delay.h>
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#include <asm/msr.h>
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#include <asm/geode.h>
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#include "gxfb.h"
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/*
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* Tables of register settings for various DOTCLKs.
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*/
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struct gx_pll_entry {
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long pixclock; /* ps */
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u32 sys_rstpll_bits;
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u32 dotpll_value;
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};
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#define POSTDIV3 ((u32)MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3)
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#define PREMULT2 ((u32)MSR_GLCP_SYS_RSTPLL_DOTPREMULT2)
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#define PREDIV2 ((u32)MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3)
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static const struct gx_pll_entry gx_pll_table_48MHz[] = {
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{ 40123, POSTDIV3, 0x00000BF2 }, /* 24.9230 */
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{ 39721, 0, 0x00000037 }, /* 25.1750 */
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{ 35308, POSTDIV3|PREMULT2, 0x00000B1A }, /* 28.3220 */
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{ 31746, POSTDIV3, 0x000002D2 }, /* 31.5000 */
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{ 27777, POSTDIV3|PREMULT2, 0x00000FE2 }, /* 36.0000 */
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{ 26666, POSTDIV3, 0x0000057A }, /* 37.5000 */
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{ 25000, POSTDIV3, 0x0000030A }, /* 40.0000 */
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{ 22271, 0, 0x00000063 }, /* 44.9000 */
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{ 20202, 0, 0x0000054B }, /* 49.5000 */
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{ 20000, 0, 0x0000026E }, /* 50.0000 */
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{ 19860, PREMULT2, 0x00000037 }, /* 50.3500 */
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{ 18518, POSTDIV3|PREMULT2, 0x00000B0D }, /* 54.0000 */
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{ 17777, 0, 0x00000577 }, /* 56.2500 */
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{ 17733, 0, 0x000007F7 }, /* 56.3916 */
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{ 17653, 0, 0x0000057B }, /* 56.6444 */
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{ 16949, PREMULT2, 0x00000707 }, /* 59.0000 */
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{ 15873, POSTDIV3|PREMULT2, 0x00000B39 }, /* 63.0000 */
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{ 15384, POSTDIV3|PREMULT2, 0x00000B45 }, /* 65.0000 */
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{ 14814, POSTDIV3|PREMULT2, 0x00000FC1 }, /* 67.5000 */
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{ 14124, POSTDIV3, 0x00000561 }, /* 70.8000 */
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{ 13888, POSTDIV3, 0x000007E1 }, /* 72.0000 */
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{ 13426, PREMULT2, 0x00000F4A }, /* 74.4810 */
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{ 13333, 0, 0x00000052 }, /* 75.0000 */
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{ 12698, 0, 0x00000056 }, /* 78.7500 */
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{ 12500, POSTDIV3|PREMULT2, 0x00000709 }, /* 80.0000 */
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{ 11135, PREMULT2, 0x00000262 }, /* 89.8000 */
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{ 10582, 0, 0x000002D2 }, /* 94.5000 */
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{ 10101, PREMULT2, 0x00000B4A }, /* 99.0000 */
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{ 10000, PREMULT2, 0x00000036 }, /* 100.0000 */
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{ 9259, 0, 0x000007E2 }, /* 108.0000 */
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{ 8888, 0, 0x000007F6 }, /* 112.5000 */
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{ 7692, POSTDIV3|PREMULT2, 0x00000FB0 }, /* 130.0000 */
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{ 7407, POSTDIV3|PREMULT2, 0x00000B50 }, /* 135.0000 */
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{ 6349, 0, 0x00000055 }, /* 157.5000 */
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{ 6172, 0, 0x000009C1 }, /* 162.0000 */
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{ 5787, PREMULT2, 0x0000002D }, /* 172.798 */
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{ 5698, 0, 0x000002C1 }, /* 175.5000 */
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{ 5291, 0, 0x000002D1 }, /* 189.0000 */
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{ 4938, 0, 0x00000551 }, /* 202.5000 */
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{ 4357, 0, 0x0000057D }, /* 229.5000 */
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};
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static const struct gx_pll_entry gx_pll_table_14MHz[] = {
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{ 39721, 0, 0x00000037 }, /* 25.1750 */
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{ 35308, 0, 0x00000B7B }, /* 28.3220 */
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{ 31746, 0, 0x000004D3 }, /* 31.5000 */
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{ 27777, 0, 0x00000BE3 }, /* 36.0000 */
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{ 26666, 0, 0x0000074F }, /* 37.5000 */
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{ 25000, 0, 0x0000050B }, /* 40.0000 */
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{ 22271, 0, 0x00000063 }, /* 44.9000 */
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{ 20202, 0, 0x0000054B }, /* 49.5000 */
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{ 20000, 0, 0x0000026E }, /* 50.0000 */
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{ 19860, 0, 0x000007C3 }, /* 50.3500 */
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{ 18518, 0, 0x000007E3 }, /* 54.0000 */
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{ 17777, 0, 0x00000577 }, /* 56.2500 */
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{ 17733, 0, 0x000002FB }, /* 56.3916 */
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{ 17653, 0, 0x0000057B }, /* 56.6444 */
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{ 16949, 0, 0x0000058B }, /* 59.0000 */
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{ 15873, 0, 0x0000095E }, /* 63.0000 */
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{ 15384, 0, 0x0000096A }, /* 65.0000 */
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{ 14814, 0, 0x00000BC2 }, /* 67.5000 */
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{ 14124, 0, 0x0000098A }, /* 70.8000 */
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{ 13888, 0, 0x00000BE2 }, /* 72.0000 */
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{ 13333, 0, 0x00000052 }, /* 75.0000 */
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{ 12698, 0, 0x00000056 }, /* 78.7500 */
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{ 12500, 0, 0x0000050A }, /* 80.0000 */
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{ 11135, 0, 0x0000078E }, /* 89.8000 */
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{ 10582, 0, 0x000002D2 }, /* 94.5000 */
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{ 10101, 0, 0x000011F6 }, /* 99.0000 */
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{ 10000, 0, 0x0000054E }, /* 100.0000 */
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{ 9259, 0, 0x000007E2 }, /* 108.0000 */
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{ 8888, 0, 0x000002FA }, /* 112.5000 */
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{ 7692, 0, 0x00000BB1 }, /* 130.0000 */
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{ 7407, 0, 0x00000975 }, /* 135.0000 */
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{ 6349, 0, 0x00000055 }, /* 157.5000 */
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{ 6172, 0, 0x000009C1 }, /* 162.0000 */
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{ 5698, 0, 0x000002C1 }, /* 175.5000 */
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{ 5291, 0, 0x00000539 }, /* 189.0000 */
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{ 4938, 0, 0x00000551 }, /* 202.5000 */
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{ 4357, 0, 0x0000057D }, /* 229.5000 */
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};
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void gx_set_dclk_frequency(struct fb_info *info)
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{
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const struct gx_pll_entry *pll_table;
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int pll_table_len;
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int i, best_i;
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long min, diff;
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u64 dotpll, sys_rstpll;
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int timeout = 1000;
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/* Rev. 1 Geode GXs use a 14 MHz reference clock instead of 48 MHz. */
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if (cpu_data(0).x86_mask == 1) {
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pll_table = gx_pll_table_14MHz;
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pll_table_len = ARRAY_SIZE(gx_pll_table_14MHz);
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} else {
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pll_table = gx_pll_table_48MHz;
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pll_table_len = ARRAY_SIZE(gx_pll_table_48MHz);
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}
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/* Search the table for the closest pixclock. */
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best_i = 0;
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min = abs(pll_table[0].pixclock - info->var.pixclock);
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for (i = 1; i < pll_table_len; i++) {
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diff = abs(pll_table[i].pixclock - info->var.pixclock);
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if (diff < min) {
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min = diff;
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best_i = i;
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}
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}
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rdmsrl(MSR_GLCP_SYS_RSTPLL, sys_rstpll);
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rdmsrl(MSR_GLCP_DOTPLL, dotpll);
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/* Program new M, N and P. */
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dotpll &= 0x00000000ffffffffull;
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dotpll |= (u64)pll_table[best_i].dotpll_value << 32;
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dotpll |= MSR_GLCP_DOTPLL_DOTRESET;
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dotpll &= ~MSR_GLCP_DOTPLL_BYPASS;
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wrmsrl(MSR_GLCP_DOTPLL, dotpll);
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/* Program dividers. */
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sys_rstpll &= ~( MSR_GLCP_SYS_RSTPLL_DOTPREDIV2
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| MSR_GLCP_SYS_RSTPLL_DOTPREMULT2
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| MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3 );
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sys_rstpll |= pll_table[best_i].sys_rstpll_bits;
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wrmsrl(MSR_GLCP_SYS_RSTPLL, sys_rstpll);
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/* Clear reset bit to start PLL. */
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dotpll &= ~(MSR_GLCP_DOTPLL_DOTRESET);
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wrmsrl(MSR_GLCP_DOTPLL, dotpll);
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/* Wait for LOCK bit. */
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do {
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rdmsrl(MSR_GLCP_DOTPLL, dotpll);
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} while (timeout-- && !(dotpll & MSR_GLCP_DOTPLL_LOCK));
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}
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static void
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gx_configure_tft(struct fb_info *info)
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{
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struct gxfb_par *par = info->par;
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unsigned long val;
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unsigned long fp;
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/* Set up the DF pad select MSR */
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rdmsrl(MSR_GX_MSR_PADSEL, val);
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val &= ~MSR_GX_MSR_PADSEL_MASK;
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val |= MSR_GX_MSR_PADSEL_TFT;
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wrmsrl(MSR_GX_MSR_PADSEL, val);
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/* Turn off the panel */
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fp = read_fp(par, FP_PM);
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fp &= ~FP_PM_P;
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write_fp(par, FP_PM, fp);
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/* Set timing 1 */
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fp = read_fp(par, FP_PT1);
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fp &= FP_PT1_VSIZE_MASK;
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fp |= info->var.yres << FP_PT1_VSIZE_SHIFT;
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write_fp(par, FP_PT1, fp);
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/* Timing 2 */
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/* Set bits that are always on for TFT */
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fp = 0x0F100000;
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/* Configure sync polarity */
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if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
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fp |= FP_PT2_VSP;
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if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
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fp |= FP_PT2_HSP;
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write_fp(par, FP_PT2, fp);
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/* Set the dither control */
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write_fp(par, FP_DFC, FP_DFC_NFI);
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/* Enable the FP data and power (in case the BIOS didn't) */
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fp = read_vp(par, VP_DCFG);
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fp |= VP_DCFG_FP_PWR_EN | VP_DCFG_FP_DATA_EN;
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write_vp(par, VP_DCFG, fp);
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/* Unblank the panel */
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fp = read_fp(par, FP_PM);
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fp |= FP_PM_P;
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write_fp(par, FP_PM, fp);
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}
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void gx_configure_display(struct fb_info *info)
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{
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struct gxfb_par *par = info->par;
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u32 dcfg, misc;
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/* Write the display configuration */
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dcfg = read_vp(par, VP_DCFG);
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/* Disable hsync and vsync */
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dcfg &= ~(VP_DCFG_VSYNC_EN | VP_DCFG_HSYNC_EN);
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write_vp(par, VP_DCFG, dcfg);
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/* Clear bits from existing mode. */
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dcfg &= ~(VP_DCFG_CRT_SYNC_SKW
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| VP_DCFG_CRT_HSYNC_POL | VP_DCFG_CRT_VSYNC_POL
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| VP_DCFG_VSYNC_EN | VP_DCFG_HSYNC_EN);
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/* Set default sync skew. */
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dcfg |= VP_DCFG_CRT_SYNC_SKW_DEFAULT;
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/* Enable hsync and vsync. */
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dcfg |= VP_DCFG_HSYNC_EN | VP_DCFG_VSYNC_EN;
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misc = read_vp(par, VP_MISC);
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/* Disable gamma correction */
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misc |= VP_MISC_GAM_EN;
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if (par->enable_crt) {
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/* Power up the CRT DACs */
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misc &= ~(VP_MISC_APWRDN | VP_MISC_DACPWRDN);
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write_vp(par, VP_MISC, misc);
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/* Only change the sync polarities if we are running
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* in CRT mode. The FP polarities will be handled in
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* gxfb_configure_tft */
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if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
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dcfg |= VP_DCFG_CRT_HSYNC_POL;
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if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
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dcfg |= VP_DCFG_CRT_VSYNC_POL;
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} else {
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/* Power down the CRT DACs if in FP mode */
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misc |= (VP_MISC_APWRDN | VP_MISC_DACPWRDN);
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write_vp(par, VP_MISC, misc);
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}
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/* Enable the display logic */
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/* Set up the DACS to blank normally */
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dcfg |= VP_DCFG_CRT_EN | VP_DCFG_DAC_BL_EN;
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/* Enable the external DAC VREF? */
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write_vp(par, VP_DCFG, dcfg);
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/* Set up the flat panel (if it is enabled) */
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if (par->enable_crt == 0)
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gx_configure_tft(info);
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}
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int gx_blank_display(struct fb_info *info, int blank_mode)
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{
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struct gxfb_par *par = info->par;
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u32 dcfg, fp_pm;
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int blank, hsync, vsync, crt;
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/* CRT power saving modes. */
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switch (blank_mode) {
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case FB_BLANK_UNBLANK:
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blank = 0; hsync = 1; vsync = 1; crt = 1;
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break;
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case FB_BLANK_NORMAL:
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blank = 1; hsync = 1; vsync = 1; crt = 1;
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break;
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case FB_BLANK_VSYNC_SUSPEND:
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blank = 1; hsync = 1; vsync = 0; crt = 1;
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break;
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case FB_BLANK_HSYNC_SUSPEND:
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blank = 1; hsync = 0; vsync = 1; crt = 1;
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break;
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case FB_BLANK_POWERDOWN:
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blank = 1; hsync = 0; vsync = 0; crt = 0;
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break;
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default:
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return -EINVAL;
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}
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dcfg = read_vp(par, VP_DCFG);
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dcfg &= ~(VP_DCFG_DAC_BL_EN | VP_DCFG_HSYNC_EN | VP_DCFG_VSYNC_EN |
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VP_DCFG_CRT_EN);
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if (!blank)
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dcfg |= VP_DCFG_DAC_BL_EN;
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if (hsync)
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dcfg |= VP_DCFG_HSYNC_EN;
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if (vsync)
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dcfg |= VP_DCFG_VSYNC_EN;
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if (crt)
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dcfg |= VP_DCFG_CRT_EN;
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write_vp(par, VP_DCFG, dcfg);
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/* Power on/off flat panel. */
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if (par->enable_crt == 0) {
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fp_pm = read_fp(par, FP_PM);
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if (blank_mode == FB_BLANK_POWERDOWN)
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fp_pm &= ~FP_PM_P;
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else
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fp_pm |= FP_PM_P;
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write_fp(par, FP_PM, fp_pm);
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}
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return 0;
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}
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