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On systems running with virtual cpus there is optimization potential in regard to spinlocks and rw-locks. If the virtual cpu that has taken a lock is known to a cpu that wants to acquire the same lock it is beneficial to yield the timeslice of the virtual cpu in favour of the cpu that has the lock (directed yield). With CONFIG_PREEMPT="n" this can be implemented by the architecture without common code changes. Powerpc already does this. With CONFIG_PREEMPT="y" the lock loops are coded with _raw_spin_trylock, _raw_read_trylock and _raw_write_trylock in kernel/spinlock.c. If the lock could not be taken cpu_relax is called. A directed yield is not possible because cpu_relax doesn't know anything about the lock. To be able to yield the lock in favour of the current lock holder variants of cpu_relax for spinlocks and rw-locks are needed. The new _raw_spin_relax, _raw_read_relax and _raw_write_relax primitives differ from cpu_relax insofar that they have an argument: a pointer to the lock structure. Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: Paul Mackerras <paulus@samba.org> Cc: Haavard Skinnemoen <hskinnemoen@atmel.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
140 lines
3.2 KiB
C
140 lines
3.2 KiB
C
#ifndef __ASM_SPINLOCK_H
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#define __ASM_SPINLOCK_H
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#include <asm/atomic.h>
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#include <asm/rwlock.h>
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#include <asm/page.h>
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#include <asm/processor.h>
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/*
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* Your basic SMP spinlocks, allowing only a single CPU anywhere
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*
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* Simple spin lock operations. There are two variants, one clears IRQ's
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* on the local processor, one does not.
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*
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* We make no fairness assumptions. They have a cost.
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*
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* (the type definitions are in asm/spinlock_types.h)
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*/
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static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
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{
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return *(volatile signed int *)(&(lock)->slock) <= 0;
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}
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static inline void __raw_spin_lock(raw_spinlock_t *lock)
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{
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asm volatile(
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"\n1:\t"
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LOCK_PREFIX " ; decl %0\n\t"
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"jns 2f\n"
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"3:\n"
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"rep;nop\n\t"
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"cmpl $0,%0\n\t"
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"jle 3b\n\t"
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"jmp 1b\n"
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"2:\t" : "=m" (lock->slock) : : "memory");
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}
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#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
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static inline int __raw_spin_trylock(raw_spinlock_t *lock)
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{
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int oldval;
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asm volatile(
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"xchgl %0,%1"
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:"=q" (oldval), "=m" (lock->slock)
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:"0" (0) : "memory");
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return oldval > 0;
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}
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static inline void __raw_spin_unlock(raw_spinlock_t *lock)
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{
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asm volatile("movl $1,%0" :"=m" (lock->slock) :: "memory");
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}
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static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock)
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{
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while (__raw_spin_is_locked(lock))
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cpu_relax();
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}
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/*
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* Read-write spinlocks, allowing multiple readers
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* but only one writer.
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*
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* NOTE! it is quite common to have readers in interrupts
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* but no interrupt writers. For those circumstances we
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* can "mix" irq-safe locks - any writer needs to get a
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* irq-safe write-lock, but readers can get non-irqsafe
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* read-locks.
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*
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* On x86, we implement read-write locks as a 32-bit counter
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* with the high bit (sign) being the "contended" bit.
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*/
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static inline int __raw_read_can_lock(raw_rwlock_t *lock)
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{
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return (int)(lock)->lock > 0;
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}
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static inline int __raw_write_can_lock(raw_rwlock_t *lock)
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{
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return (lock)->lock == RW_LOCK_BIAS;
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}
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static inline void __raw_read_lock(raw_rwlock_t *rw)
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{
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asm volatile(LOCK_PREFIX "subl $1,(%0)\n\t"
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"jns 1f\n"
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"call __read_lock_failed\n"
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"1:\n"
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::"D" (rw), "i" (RW_LOCK_BIAS) : "memory");
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}
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static inline void __raw_write_lock(raw_rwlock_t *rw)
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{
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asm volatile(LOCK_PREFIX "subl %1,(%0)\n\t"
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"jz 1f\n"
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"\tcall __write_lock_failed\n\t"
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"1:\n"
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::"D" (rw), "i" (RW_LOCK_BIAS) : "memory");
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}
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static inline int __raw_read_trylock(raw_rwlock_t *lock)
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{
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atomic_t *count = (atomic_t *)lock;
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atomic_dec(count);
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if (atomic_read(count) >= 0)
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return 1;
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atomic_inc(count);
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return 0;
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}
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static inline int __raw_write_trylock(raw_rwlock_t *lock)
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{
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atomic_t *count = (atomic_t *)lock;
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if (atomic_sub_and_test(RW_LOCK_BIAS, count))
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return 1;
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atomic_add(RW_LOCK_BIAS, count);
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return 0;
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}
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static inline void __raw_read_unlock(raw_rwlock_t *rw)
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{
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asm volatile(LOCK_PREFIX " ; incl %0" :"=m" (rw->lock) : : "memory");
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}
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static inline void __raw_write_unlock(raw_rwlock_t *rw)
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{
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asm volatile(LOCK_PREFIX " ; addl $" RW_LOCK_BIAS_STR ",%0"
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: "=m" (rw->lock) : : "memory");
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}
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#define _raw_spin_relax(lock) cpu_relax()
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#define _raw_read_relax(lock) cpu_relax()
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#define _raw_write_relax(lock) cpu_relax()
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#endif /* __ASM_SPINLOCK_H */
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