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f45e518361
Along the lines of d6c585a434, add IRQF_TIMER
flag for all timer interrupts This ensures that timer interrupts won't be
disabled on suspend and not threaded for PREEMPT_RT.
Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
140 lines
3.6 KiB
C
140 lines
3.6 KiB
C
/*
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* GT641xx clockevent routines.
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*
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* Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/clockchips.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <asm/gt64120.h>
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#include <asm/time.h>
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static DEFINE_SPINLOCK(gt641xx_timer_lock);
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static unsigned int gt641xx_base_clock;
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void gt641xx_set_base_clock(unsigned int clock)
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{
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gt641xx_base_clock = clock;
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}
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int gt641xx_timer0_state(void)
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{
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if (GT_READ(GT_TC0_OFS))
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return 0;
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GT_WRITE(GT_TC0_OFS, gt641xx_base_clock / HZ);
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GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK);
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return 1;
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}
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static int gt641xx_timer0_set_next_event(unsigned long delta,
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struct clock_event_device *evt)
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{
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u32 ctrl;
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spin_lock(>641xx_timer_lock);
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ctrl = GT_READ(GT_TC_CONTROL_OFS);
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ctrl &= ~(GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
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ctrl |= GT_TC_CONTROL_ENTC0_MSK;
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GT_WRITE(GT_TC0_OFS, delta);
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GT_WRITE(GT_TC_CONTROL_OFS, ctrl);
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spin_unlock(>641xx_timer_lock);
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return 0;
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}
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static void gt641xx_timer0_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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u32 ctrl;
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spin_lock(>641xx_timer_lock);
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ctrl = GT_READ(GT_TC_CONTROL_OFS);
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ctrl &= ~(GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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ctrl |= GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK;
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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ctrl |= GT_TC_CONTROL_ENTC0_MSK;
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break;
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default:
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break;
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}
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GT_WRITE(GT_TC_CONTROL_OFS, ctrl);
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spin_unlock(>641xx_timer_lock);
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}
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static void gt641xx_timer0_event_handler(struct clock_event_device *dev)
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{
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}
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static struct clock_event_device gt641xx_timer0_clockevent = {
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.name = "gt641xx-timer0",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.irq = GT641XX_TIMER0_IRQ,
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.set_next_event = gt641xx_timer0_set_next_event,
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.set_mode = gt641xx_timer0_set_mode,
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.event_handler = gt641xx_timer0_event_handler,
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};
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static irqreturn_t gt641xx_timer0_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *cd = >641xx_timer0_clockevent;
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cd->event_handler(cd);
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return IRQ_HANDLED;
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}
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static struct irqaction gt641xx_timer0_irqaction = {
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.handler = gt641xx_timer0_interrupt,
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.flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER,
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.name = "gt641xx_timer0",
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};
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static int __init gt641xx_timer0_clockevent_init(void)
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{
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struct clock_event_device *cd;
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if (!gt641xx_base_clock)
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return 0;
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GT_WRITE(GT_TC0_OFS, gt641xx_base_clock / HZ);
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cd = >641xx_timer0_clockevent;
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cd->rating = 200 + gt641xx_base_clock / 10000000;
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clockevent_set_clock(cd, gt641xx_base_clock);
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cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
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cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
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cd->cpumask = cpumask_of(0);
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clockevents_register_device(>641xx_timer0_clockevent);
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return setup_irq(GT641XX_TIMER0_IRQ, >641xx_timer0_irqaction);
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}
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arch_initcall(gt641xx_timer0_clockevent_init);
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