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per cpu data section contains two types of data. One set which is exclusively accessed by the local cpu and the other set which is per cpu, but also shared by remote cpus. In the current kernel, these two sets are not clearely separated out. This can potentially cause the same data cacheline shared between the two sets of data, which will result in unnecessary bouncing of the cacheline between cpus. One way to fix the problem is to cacheline align the remotely accessed per cpu data, both at the beginning and at the end. Because of the padding at both ends, this will likely cause some memory wastage and also the interface to achieve this is not clean. This patch: Moves the remotely accessed per cpu data (which is currently marked as ____cacheline_aligned_in_smp) into a different section, where all the data elements are cacheline aligned. And as such, this differentiates the local only data and remotely accessed data cleanly. Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Acked-by: Suresh Siddha <suresh.b.siddha@intel.com> Cc: Rusty Russell <rusty@rustcorp.com.au> Cc: Christoph Lameter <clameter@sgi.com> Cc: <linux-arch@vger.kernel.org> Cc: "Luck, Tony" <tony.luck@intel.com> Cc: Andi Kleen <ak@suse.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> |
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| arc | ||
| au1000 | ||
| basler/excite | ||
| boot | ||
| cobalt | ||
| configs | ||
| ddb5xxx | ||
| dec | ||
| emma2rh | ||
| gt64120 | ||
| jazz | ||
| jmr3927 | ||
| kernel | ||
| lemote/lm2e | ||
| lib | ||
| math-emu | ||
| mips-boards | ||
| mipssim | ||
| mm | ||
| oprofile | ||
| pci | ||
| philips/pnx8550 | ||
| pmc-sierra | ||
| qemu | ||
| sgi-ip22 | ||
| sgi-ip27 | ||
| sgi-ip32 | ||
| sibyte | ||
| sni | ||
| tx4927 | ||
| tx4938 | ||
| vr41xx | ||
| defconfig | ||
| Kconfig | ||
| Kconfig.debug | ||
| Makefile | ||