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The attached patches provides part 6 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
25 lines
644 B
C
25 lines
644 B
C
/*
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* include/asm-xtensa/tlb.h
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001 - 2005 Tensilica Inc.
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*/
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#ifndef _XTENSA_TLB_H
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#define _XTENSA_TLB_H
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#define tlb_start_vma(tlb,vma) do { } while (0)
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#define tlb_end_vma(tlb,vma) do { } while (0)
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#define __tlb_remove_tlb_entry(tlb,pte,addr) do { } while (0)
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#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
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#include <asm-generic/tlb.h>
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#include <asm/page.h>
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#define __pte_free_tlb(tlb,pte) pte_free(pte)
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#endif /* _XTENSA_TLB_H */
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