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The attached patches provides part 6 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
135 lines
3.6 KiB
Text
135 lines
3.6 KiB
Text
/*
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* linux/include/asm-xtensa/page.h
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version2 as
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* published by the Free Software Foundation.
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*
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* Copyright (C) 2001 - 2005 Tensilica Inc.
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*/
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#ifndef _XTENSA_PAGE_H
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#define _XTENSA_PAGE_H
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#ifdef __KERNEL__
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#include <asm/processor.h>
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#include <linux/config.h>
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/*
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* PAGE_SHIFT determines the page size
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* PAGE_ALIGN(x) aligns the pointer to the (next) page boundary
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*/
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#define PAGE_SHIFT XCHAL_MMU_MIN_PTE_PAGE_SIZE
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#define PAGE_SIZE (1 << PAGE_SHIFT)
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#define PAGE_MASK (~(PAGE_SIZE-1))
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#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE - 1) & PAGE_MASK)
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#define DCACHE_WAY_SIZE (XCHAL_DCACHE_SIZE / XCHAL_DCACHE_WAYS)
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#define PAGE_OFFSET XCHAL_KSEG_CACHED_VADDR
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#ifdef __ASSEMBLY__
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#define __pgprot(x) (x)
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#else
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/*
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* These are used to make use of C type-checking..
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*/
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typedef struct { unsigned long pte; } pte_t; /* page table entry */
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typedef struct { unsigned long pmd; } pmd_t; /* PMD table entry */
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typedef struct { unsigned long pgd; } pgd_t; /* PGD table entry */
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typedef struct { unsigned long pgprot; } pgprot_t;
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#define pte_val(x) ((x).pte)
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#define pmd_val(x) ((x).pmd)
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#define pgd_val(x) ((x).pgd)
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#define pgprot_val(x) ((x).pgprot)
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#define __pte(x) ((pte_t) { (x) } )
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#define __pmd(x) ((pmd_t) { (x) } )
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#define __pgd(x) ((pgd_t) { (x) } )
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#define __pgprot(x) ((pgprot_t) { (x) } )
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/*
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* Pure 2^n version of get_order
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*/
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extern __inline__ int get_order(unsigned long size)
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{
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int order;
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#ifndef XCHAL_HAVE_NSU
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unsigned long x1, x2, x4, x8, x16;
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size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
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x1 = size & 0xAAAAAAAA;
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x2 = size & 0xCCCCCCCC;
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x4 = size & 0xF0F0F0F0;
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x8 = size & 0xFF00FF00;
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x16 = size & 0xFFFF0000;
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order = x2 ? 2 : 0;
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order += (x16 != 0) * 16;
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order += (x8 != 0) * 8;
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order += (x4 != 0) * 4;
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order += (x1 != 0);
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return order;
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#else
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size = (size - 1) >> PAGE_SHIFT;
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asm ("nsau %0, %1" : "=r" (order) : "r" (size));
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return 32 - order;
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#endif
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}
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struct page;
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extern void clear_page(void *page);
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extern void copy_page(void *to, void *from);
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/*
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* If we have cache aliasing and writeback caches, we might have to do
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* some extra work
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*/
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#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
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void clear_user_page(void *addr, unsigned long vaddr, struct page* page);
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void copy_user_page(void *to, void* from, unsigned long vaddr, struct page* page);
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#else
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# define clear_user_page(page,vaddr,pg) clear_page(page)
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# define copy_user_page(to, from, vaddr, pg) copy_page(to, from)
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#endif
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/*
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* This handles the memory map. We handle pages at
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* XCHAL_KSEG_CACHED_VADDR for kernels with 32 bit address space.
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* These macros are for conversion of kernel address, not user
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* addresses.
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*/
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#define __pa(x) ((unsigned long) (x) - PAGE_OFFSET)
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#define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET))
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#define pfn_valid(pfn) ((unsigned long)pfn < max_mapnr)
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#ifndef CONFIG_DISCONTIGMEM
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# define pfn_to_page(pfn) (mem_map + (pfn))
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# define page_to_pfn(page) ((unsigned long)((page) - mem_map))
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#else
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# error CONFIG_DISCONTIGMEM not supported
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#endif
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#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
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#define page_to_virt(page) __va(page_to_pfn(page) << PAGE_SHIFT)
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#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
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#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
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#define WANT_PAGE_VIRTUAL
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#endif /* __ASSEMBLY__ */
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#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
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VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
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#endif /* __KERNEL__ */
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#endif /* _XTENSA_PAGE_H */
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