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1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
112 lines
4.7 KiB
C
112 lines
4.7 KiB
C
/* $Id: asi.h,v 1.18 1998/03/09 14:04:46 jj Exp $ */
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#ifndef _SPARC_ASI_H
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#define _SPARC_ASI_H
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/* asi.h: Address Space Identifier values for the sparc.
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*
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* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
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*
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* Pioneer work for sun4m: Paul Hatchman (paul@sfe.com.au)
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* Joint edition for sun4c+sun4m: Pete A. Zaitcev <zaitcev@ipmce.su>
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*/
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/* The first batch are for the sun4c. */
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#define ASI_NULL1 0x00
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#define ASI_NULL2 0x01
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/* sun4c and sun4 control registers and mmu/vac ops */
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#define ASI_CONTROL 0x02
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#define ASI_SEGMAP 0x03
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#define ASI_PTE 0x04
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#define ASI_HWFLUSHSEG 0x05
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#define ASI_HWFLUSHPAGE 0x06
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#define ASI_REGMAP 0x06
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#define ASI_HWFLUSHCONTEXT 0x07
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#define ASI_USERTXT 0x08
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#define ASI_KERNELTXT 0x09
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#define ASI_USERDATA 0x0a
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#define ASI_KERNELDATA 0x0b
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/* VAC Cache flushing on sun4c and sun4 */
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#define ASI_FLUSHSEG 0x0c
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#define ASI_FLUSHPG 0x0d
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#define ASI_FLUSHCTX 0x0e
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/* SPARCstation-5: only 6 bits are decoded. */
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/* wo = Write Only, rw = Read Write; */
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/* ss = Single Size, as = All Sizes; */
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#define ASI_M_RES00 0x00 /* Don't touch... */
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#define ASI_M_UNA01 0x01 /* Same here... */
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#define ASI_M_MXCC 0x02 /* Access to TI VIKING MXCC registers */
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#define ASI_M_FLUSH_PROBE 0x03 /* Reference MMU Flush/Probe; rw, ss */
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#define ASI_M_MMUREGS 0x04 /* MMU Registers; rw, ss */
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#define ASI_M_TLBDIAG 0x05 /* MMU TLB only Diagnostics */
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#define ASI_M_DIAGS 0x06 /* Reference MMU Diagnostics */
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#define ASI_M_IODIAG 0x07 /* MMU I/O TLB only Diagnostics */
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#define ASI_M_USERTXT 0x08 /* Same as ASI_USERTXT; rw, as */
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#define ASI_M_KERNELTXT 0x09 /* Same as ASI_KERNELTXT; rw, as */
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#define ASI_M_USERDATA 0x0A /* Same as ASI_USERDATA; rw, as */
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#define ASI_M_KERNELDATA 0x0B /* Same as ASI_KERNELDATA; rw, as */
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#define ASI_M_TXTC_TAG 0x0C /* Instruction Cache Tag; rw, ss */
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#define ASI_M_TXTC_DATA 0x0D /* Instruction Cache Data; rw, ss */
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#define ASI_M_DATAC_TAG 0x0E /* Data Cache Tag; rw, ss */
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#define ASI_M_DATAC_DATA 0x0F /* Data Cache Data; rw, ss */
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/* The following cache flushing ASIs work only with the 'sta'
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* instruction. Results are unpredictable for 'swap' and 'ldstuba',
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* so don't do it.
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*/
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/* These ASI flushes affect external caches too. */
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#define ASI_M_FLUSH_PAGE 0x10 /* Flush I&D Cache Line (page); wo, ss */
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#define ASI_M_FLUSH_SEG 0x11 /* Flush I&D Cache Line (seg); wo, ss */
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#define ASI_M_FLUSH_REGION 0x12 /* Flush I&D Cache Line (region); wo, ss */
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#define ASI_M_FLUSH_CTX 0x13 /* Flush I&D Cache Line (context); wo, ss */
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#define ASI_M_FLUSH_USER 0x14 /* Flush I&D Cache Line (user); wo, ss */
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/* Block-copy operations are available only on certain V8 cpus. */
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#define ASI_M_BCOPY 0x17 /* Block copy */
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/* These affect only the ICACHE and are Ross HyperSparc and TurboSparc specific. */
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#define ASI_M_IFLUSH_PAGE 0x18 /* Flush I Cache Line (page); wo, ss */
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#define ASI_M_IFLUSH_SEG 0x19 /* Flush I Cache Line (seg); wo, ss */
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#define ASI_M_IFLUSH_REGION 0x1A /* Flush I Cache Line (region); wo, ss */
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#define ASI_M_IFLUSH_CTX 0x1B /* Flush I Cache Line (context); wo, ss */
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#define ASI_M_IFLUSH_USER 0x1C /* Flush I Cache Line (user); wo, ss */
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/* Block-fill operations are available on certain V8 cpus */
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#define ASI_M_BFILL 0x1F
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/* This allows direct access to main memory, actually 0x20 to 0x2f are
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* the available ASI's for physical ram pass-through, but I don't have
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* any idea what the other ones do....
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*/
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#define ASI_M_BYPASS 0x20 /* Reference MMU bypass; rw, as */
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#define ASI_M_FBMEM 0x29 /* Graphics card frame buffer access */
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#define ASI_M_VMEUS 0x2A /* VME user 16-bit access */
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#define ASI_M_VMEPS 0x2B /* VME priv 16-bit access */
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#define ASI_M_VMEUT 0x2C /* VME user 32-bit access */
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#define ASI_M_VMEPT 0x2D /* VME priv 32-bit access */
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#define ASI_M_SBUS 0x2E /* Direct SBus access */
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#define ASI_M_CTL 0x2F /* Control Space (ECC and MXCC are here) */
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/* This is ROSS HyperSparc only. */
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#define ASI_M_FLUSH_IWHOLE 0x31 /* Flush entire ICACHE; wo, ss */
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/* Tsunami/Viking/TurboSparc i/d cache flash clear. */
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#define ASI_M_IC_FLCLEAR 0x36
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#define ASI_M_DC_FLCLEAR 0x37
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#define ASI_M_DCDR 0x39 /* Data Cache Diagnostics Register rw, ss */
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#define ASI_M_VIKING_TMP1 0x40 /* Emulation temporary 1 on Viking */
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/* only available on SuperSparc I */
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/* #define ASI_M_VIKING_TMP2 0x41 */ /* Emulation temporary 2 on Viking */
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#define ASI_M_ACTION 0x4c /* Breakpoint Action Register (GNU/Viking) */
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#endif /* _SPARC_ASI_H */
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