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de957628ce
This changes gart_iommu_hole_init() to set gart_iommu_init() to iommu_init hook if gart_iommu_hole_init() finds the GART IOMMU. We can kill the code to check if we found the IOMMU in gart_iommu_init() since gart_iommu_hole_init() sets gart_iommu_init() only when it found the IOMMU. Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Cc: chrisw@sous-sol.org Cc: dwmw2@infradead.org Cc: joerg.roedel@amd.com Cc: muli@il.ibm.com LKML-Reference: <1257849980-22640-4-git-send-email-fujita.tomonori@lab.ntt.co.jp> Signed-off-by: Ingo Molnar <mingo@elte.hu>
99 lines
2.3 KiB
C
99 lines
2.3 KiB
C
#ifndef _ASM_X86_GART_H
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#define _ASM_X86_GART_H
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#include <asm/e820.h>
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extern void set_up_gart_resume(u32, u32);
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extern int fallback_aper_order;
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extern int fallback_aper_force;
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extern int fix_aperture;
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/* PTE bits. */
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#define GPTE_VALID 1
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#define GPTE_COHERENT 2
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/* Aperture control register bits. */
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#define GARTEN (1<<0)
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#define DISGARTCPU (1<<4)
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#define DISGARTIO (1<<5)
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/* GART cache control register bits. */
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#define INVGART (1<<0)
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#define GARTPTEERR (1<<1)
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/* K8 On-cpu GART registers */
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#define AMD64_GARTAPERTURECTL 0x90
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#define AMD64_GARTAPERTUREBASE 0x94
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#define AMD64_GARTTABLEBASE 0x98
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#define AMD64_GARTCACHECTL 0x9c
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#define AMD64_GARTEN (1<<0)
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#ifdef CONFIG_GART_IOMMU
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extern int gart_iommu_aperture;
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extern int gart_iommu_aperture_allowed;
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extern int gart_iommu_aperture_disabled;
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extern void early_gart_iommu_check(void);
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extern int gart_iommu_init(void);
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extern void __init gart_parse_options(char *);
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extern void gart_iommu_hole_init(void);
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#else
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#define gart_iommu_aperture 0
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#define gart_iommu_aperture_allowed 0
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#define gart_iommu_aperture_disabled 1
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static inline void early_gart_iommu_check(void)
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{
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}
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static inline void gart_parse_options(char *options)
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{
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}
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static inline void gart_iommu_hole_init(void)
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{
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}
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#endif
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extern int agp_amd64_init(void);
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static inline void enable_gart_translation(struct pci_dev *dev, u64 addr)
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{
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u32 tmp, ctl;
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/* address of the mappings table */
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addr >>= 12;
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tmp = (u32) addr<<4;
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tmp &= ~0xf;
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pci_write_config_dword(dev, AMD64_GARTTABLEBASE, tmp);
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/* Enable GART translation for this hammer. */
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pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
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ctl |= GARTEN;
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ctl &= ~(DISGARTCPU | DISGARTIO);
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pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
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}
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static inline int aperture_valid(u64 aper_base, u32 aper_size, u32 min_size)
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{
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if (!aper_base)
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return 0;
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if (aper_base + aper_size > 0x100000000ULL) {
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printk(KERN_INFO "Aperture beyond 4GB. Ignoring.\n");
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return 0;
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}
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if (e820_any_mapped(aper_base, aper_base + aper_size, E820_RAM)) {
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printk(KERN_INFO "Aperture pointing to e820 RAM. Ignoring.\n");
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return 0;
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}
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if (aper_size < min_size) {
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printk(KERN_INFO "Aperture too small (%d MB) than (%d MB)\n",
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aper_size>>20, min_size>>20);
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return 0;
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}
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return 1;
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}
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#endif /* _ASM_X86_GART_H */
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