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e7300d04bd
Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
144 lines
3.2 KiB
C
144 lines
3.2 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <linux/log2.h>
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#include <bcm63xx_cpu.h>
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#include <bcm63xx_io.h>
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#include <bcm63xx_regs.h>
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#include <bcm63xx_cs.h>
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static DEFINE_SPINLOCK(bcm63xx_cs_lock);
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/*
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* check if given chip select exists
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*/
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static int is_valid_cs(unsigned int cs)
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{
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if (cs > 6)
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return 0;
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return 1;
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}
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/*
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* Configure chipselect base address and size (bytes).
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* Size must be a power of two between 8k and 256M.
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*/
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int bcm63xx_set_cs_base(unsigned int cs, u32 base, unsigned int size)
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{
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unsigned long flags;
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u32 val;
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if (!is_valid_cs(cs))
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return -EINVAL;
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/* sanity check on size */
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if (size != roundup_pow_of_two(size))
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return -EINVAL;
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if (size < 8 * 1024 || size > 256 * 1024 * 1024)
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return -EINVAL;
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val = (base & MPI_CSBASE_BASE_MASK);
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/* 8k => 0 - 256M => 15 */
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val |= (ilog2(size) - ilog2(8 * 1024)) << MPI_CSBASE_SIZE_SHIFT;
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spin_lock_irqsave(&bcm63xx_cs_lock, flags);
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bcm_mpi_writel(val, MPI_CSBASE_REG(cs));
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spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(bcm63xx_set_cs_base);
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/*
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* configure chipselect timing (ns)
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*/
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int bcm63xx_set_cs_timing(unsigned int cs, unsigned int wait,
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unsigned int setup, unsigned int hold)
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{
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unsigned long flags;
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u32 val;
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if (!is_valid_cs(cs))
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return -EINVAL;
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spin_lock_irqsave(&bcm63xx_cs_lock, flags);
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val = bcm_mpi_readl(MPI_CSCTL_REG(cs));
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val &= ~(MPI_CSCTL_WAIT_MASK);
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val &= ~(MPI_CSCTL_SETUP_MASK);
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val &= ~(MPI_CSCTL_HOLD_MASK);
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val |= wait << MPI_CSCTL_WAIT_SHIFT;
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val |= setup << MPI_CSCTL_SETUP_SHIFT;
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val |= hold << MPI_CSCTL_HOLD_SHIFT;
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bcm_mpi_writel(val, MPI_CSCTL_REG(cs));
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spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(bcm63xx_set_cs_timing);
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/*
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* configure other chipselect parameter (data bus size, ...)
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*/
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int bcm63xx_set_cs_param(unsigned int cs, u32 params)
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{
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unsigned long flags;
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u32 val;
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if (!is_valid_cs(cs))
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return -EINVAL;
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/* none of this fields apply to pcmcia */
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if (cs == MPI_CS_PCMCIA_COMMON ||
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cs == MPI_CS_PCMCIA_ATTR ||
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cs == MPI_CS_PCMCIA_IO)
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return -EINVAL;
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spin_lock_irqsave(&bcm63xx_cs_lock, flags);
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val = bcm_mpi_readl(MPI_CSCTL_REG(cs));
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val &= ~(MPI_CSCTL_DATA16_MASK);
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val &= ~(MPI_CSCTL_SYNCMODE_MASK);
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val &= ~(MPI_CSCTL_TSIZE_MASK);
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val &= ~(MPI_CSCTL_ENDIANSWAP_MASK);
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val |= params;
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bcm_mpi_writel(val, MPI_CSCTL_REG(cs));
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spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(bcm63xx_set_cs_param);
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/*
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* set cs status (enable/disable)
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*/
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int bcm63xx_set_cs_status(unsigned int cs, int enable)
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{
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unsigned long flags;
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u32 val;
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if (!is_valid_cs(cs))
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return -EINVAL;
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spin_lock_irqsave(&bcm63xx_cs_lock, flags);
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val = bcm_mpi_readl(MPI_CSCTL_REG(cs));
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if (enable)
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val |= MPI_CSCTL_ENABLE_MASK;
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else
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val &= ~MPI_CSCTL_ENABLE_MASK;
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bcm_mpi_writel(val, MPI_CSCTL_REG(cs));
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spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(bcm63xx_set_cs_status);
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