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86027ae78c
When setting WM8510_MCLKDIV the pll was turned off. When setting pll frequency you got twice the expected freq, because the code calculated with postscaler of 8, but the hardware divide by 4. Signed-off-by: Jonas Andersson <jonas@microbit.se> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> |
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| .. | ||
| atmel | ||
| au1x | ||
| blackfin | ||
| codecs | ||
| davinci | ||
| fsl | ||
| omap | ||
| pxa | ||
| s3c24xx | ||
| sh | ||
| Kconfig | ||
| Makefile | ||
| soc-core.c | ||
| soc-dapm.c | ||
| soc-jack.c | ||