mirror of
https://github.com/adulau/aha.git
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1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
286 lines
7.7 KiB
C
286 lines
7.7 KiB
C
/*
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* linux/drivers/video/retz3fb.h -- Defines and macros for the RetinaZ3 frame
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* buffer device
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*
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* Copyright (C) 1997 Jes Sorensen
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*
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* History:
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* - 22 Jan 97: Initial work
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*
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
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*/
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/*
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* Macros to read and write to registers.
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*/
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#define reg_w(regs, reg,dat) (*(regs + reg) = dat)
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#define reg_r(regs, reg) (*(regs + reg))
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/*
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* Macro to access the sequencer.
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*/
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#define seq_w(regs, sreg, sdat) \
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do{ reg_w(regs, SEQ_IDX, sreg); reg_w(regs, SEQ_DATA, sdat); } while(0)
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/*
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* Macro to access the CRT controller.
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*/
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#define crt_w(regs, creg, cdat) \
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do{ reg_w(regs, CRT_IDX, creg); reg_w(regs, CRT_DATA, cdat); } while(0)
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/*
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* Macro to access the graphics controller.
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*/
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#define gfx_w(regs, greg, gdat) \
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do{ reg_w(regs, GFX_IDX, greg); reg_w(regs, GFX_DATA, gdat); } while(0)
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/*
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* Macro to access the attribute controller.
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*/
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#define attr_w(regs, areg, adat) \
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do{ reg_w(regs, ACT_IDX, areg); reg_w(regs, ACT_DATA, adat); } while(0)
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/*
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* Macro to access the pll.
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*/
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#define pll_w(regs, preg, pdat) \
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do{ reg_w(regs, PLL_IDX, preg); \
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reg_w(regs, PLL_DATA, (pdat & 0xff)); \
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reg_w(regs, PLL_DATA, (pdat >> 8));\
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} while(0)
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/*
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* Offsets
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*/
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#define VIDEO_MEM_OFFSET 0x00c00000
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#define ACM_OFFSET 0x00b00000
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/*
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* Accelerator Control Menu
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*/
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#define ACM_PRIMARY_OFFSET 0x00
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#define ACM_SECONDARY_OFFSET 0x04
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#define ACM_MODE_CONTROL 0x08
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#define ACM_CURSOR_POSITION 0x0c
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#define ACM_START_STATUS 0x30
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#define ACM_CONTROL 0x34
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#define ACM_RASTEROP_ROTATION 0x38
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#define ACM_BITMAP_DIMENSION 0x3c
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#define ACM_DESTINATION 0x40
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#define ACM_SOURCE 0x44
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#define ACM_PATTERN 0x48
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#define ACM_FOREGROUND 0x4c
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#define ACM_BACKGROUND 0x50
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/*
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* Video DAC addresses
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*/
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#define VDAC_ADDRESS 0x03c8
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#define VDAC_ADDRESS_W 0x03c8
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#define VDAC_ADDRESS_R 0x03c7
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#define VDAC_STATE 0x03c7
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#define VDAC_DATA 0x03c9
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#define VDAC_MASK 0x03c6
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/*
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* Sequencer
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*/
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#define SEQ_IDX 0x03c4 /* Sequencer Index */
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#define SEQ_DATA 0x03c5
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#define SEQ_RESET 0x00
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#define SEQ_CLOCKING_MODE 0x01
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#define SEQ_MAP_MASK 0x02
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#define SEQ_CHAR_MAP_SELECT 0x03
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#define SEQ_MEMORY_MODE 0x04
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#define SEQ_EXTENDED_ENABLE 0x05 /* NCR extensions */
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#define SEQ_UNKNOWN1 0x06
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#define SEQ_UNKNOWN2 0x07
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#define SEQ_CHIP_ID 0x08
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#define SEQ_UNKNOWN3 0x09
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#define SEQ_CURSOR_COLOR1 0x0a
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#define SEQ_CURSOR_COLOR0 0x0b
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#define SEQ_CURSOR_CONTROL 0x0c
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#define SEQ_CURSOR_X_LOC_HI 0x0d
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#define SEQ_CURSOR_X_LOC_LO 0x0e
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#define SEQ_CURSOR_Y_LOC_HI 0x0f
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#define SEQ_CURSOR_Y_LOC_LO 0x10
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#define SEQ_CURSOR_X_INDEX 0x11
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#define SEQ_CURSOR_Y_INDEX 0x12
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#define SEQ_CURSOR_STORE_HI 0x13
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#define SEQ_CURSOR_STORE_LO 0x14
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#define SEQ_CURSOR_ST_OFF_HI 0x15
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#define SEQ_CURSOR_ST_OFF_LO 0x16
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#define SEQ_CURSOR_PIXELMASK 0x17
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#define SEQ_PRIM_HOST_OFF_HI 0x18
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#define SEQ_PRIM_HOST_OFF_LO 0x19
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#define SEQ_LINEAR_0 0x1a
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#define SEQ_LINEAR_1 0x1b
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#define SEQ_SEC_HOST_OFF_HI 0x1c
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#define SEQ_SEC_HOST_OFF_LO 0x1d
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#define SEQ_EXTENDED_MEM_ENA 0x1e
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#define SEQ_EXT_CLOCK_MODE 0x1f
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#define SEQ_EXT_VIDEO_ADDR 0x20
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#define SEQ_EXT_PIXEL_CNTL 0x21
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#define SEQ_BUS_WIDTH_FEEDB 0x22
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#define SEQ_PERF_SELECT 0x23
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#define SEQ_COLOR_EXP_WFG 0x24
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#define SEQ_COLOR_EXP_WBG 0x25
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#define SEQ_EXT_RW_CONTROL 0x26
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#define SEQ_MISC_FEATURE_SEL 0x27
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#define SEQ_COLOR_KEY_CNTL 0x28
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#define SEQ_COLOR_KEY_MATCH0 0x29
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#define SEQ_COLOR_KEY_MATCH1 0x2a
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#define SEQ_COLOR_KEY_MATCH2 0x2b
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#define SEQ_UNKNOWN6 0x2c
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#define SEQ_CRC_CONTROL 0x2d
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#define SEQ_CRC_DATA_LOW 0x2e
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#define SEQ_CRC_DATA_HIGH 0x2f
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#define SEQ_MEMORY_MAP_CNTL 0x30
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#define SEQ_ACM_APERTURE_1 0x31
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#define SEQ_ACM_APERTURE_2 0x32
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#define SEQ_ACM_APERTURE_3 0x33
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#define SEQ_BIOS_UTILITY_0 0x3e
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#define SEQ_BIOS_UTILITY_1 0x3f
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/*
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* Graphics Controller
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*/
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#define GFX_IDX 0x03ce
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#define GFX_DATA 0x03cf
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#define GFX_SET_RESET 0x00
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#define GFX_ENABLE_SET_RESET 0x01
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#define GFX_COLOR_COMPARE 0x02
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#define GFX_DATA_ROTATE 0x03
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#define GFX_READ_MAP_SELECT 0x04
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#define GFX_GRAPHICS_MODE 0x05
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#define GFX_MISC 0x06
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#define GFX_COLOR_XCARE 0x07
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#define GFX_BITMASK 0x08
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/*
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* CRT Controller
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*/
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#define CRT_IDX 0x03d4
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#define CRT_DATA 0x03d5
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#define CRT_HOR_TOTAL 0x00
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#define CRT_HOR_DISP_ENA_END 0x01
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#define CRT_START_HOR_BLANK 0x02
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#define CRT_END_HOR_BLANK 0x03
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#define CRT_START_HOR_RETR 0x04
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#define CRT_END_HOR_RETR 0x05
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#define CRT_VER_TOTAL 0x06
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#define CRT_OVERFLOW 0x07
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#define CRT_PRESET_ROW_SCAN 0x08
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#define CRT_MAX_SCAN_LINE 0x09
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#define CRT_CURSOR_START 0x0a
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#define CRT_CURSOR_END 0x0b
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#define CRT_START_ADDR_HIGH 0x0c
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#define CRT_START_ADDR_LOW 0x0d
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#define CRT_CURSOR_LOC_HIGH 0x0e
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#define CRT_CURSOR_LOC_LOW 0x0f
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#define CRT_START_VER_RETR 0x10
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#define CRT_END_VER_RETR 0x11
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#define CRT_VER_DISP_ENA_END 0x12
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#define CRT_OFFSET 0x13
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#define CRT_UNDERLINE_LOC 0x14
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#define CRT_START_VER_BLANK 0x15
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#define CRT_END_VER_BLANK 0x16
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#define CRT_MODE_CONTROL 0x17
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#define CRT_LINE_COMPARE 0x18
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#define CRT_UNKNOWN1 0x19
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#define CRT_UNKNOWN2 0x1a
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#define CRT_UNKNOWN3 0x1b
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#define CRT_UNKNOWN4 0x1c
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#define CRT_UNKNOWN5 0x1d
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#define CRT_UNKNOWN6 0x1e
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#define CRT_UNKNOWN7 0x1f
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#define CRT_UNKNOWN8 0x20
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#define CRT_UNKNOWN9 0x21
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#define CRT_UNKNOWN10 0x22
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#define CRT_UNKNOWN11 0x23
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#define CRT_UNKNOWN12 0x24
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#define CRT_UNKNOWN13 0x25
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#define CRT_UNKNOWN14 0x26
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#define CRT_UNKNOWN15 0x27
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#define CRT_UNKNOWN16 0x28
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#define CRT_UNKNOWN17 0x29
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#define CRT_UNKNOWN18 0x2a
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#define CRT_UNKNOWN19 0x2b
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#define CRT_UNKNOWN20 0x2c
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#define CRT_UNKNOWN21 0x2d
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#define CRT_UNKNOWN22 0x2e
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#define CRT_UNKNOWN23 0x2f
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#define CRT_EXT_HOR_TIMING1 0x30 /* NCR crt extensions */
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#define CRT_EXT_START_ADDR 0x31
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#define CRT_EXT_HOR_TIMING2 0x32
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#define CRT_EXT_VER_TIMING 0x33
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#define CRT_MONITOR_POWER 0x34
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/*
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* General Registers
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*/
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#define GREG_STATUS0_R 0x03c2
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#define GREG_STATUS1_R 0x03da
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#define GREG_MISC_OUTPUT_R 0x03cc
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#define GREG_MISC_OUTPUT_W 0x03c2
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#define GREG_FEATURE_CONTROL_R 0x03ca
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#define GREG_FEATURE_CONTROL_W 0x03da
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#define GREG_POS 0x0102
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/*
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* Attribute Controller
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*/
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#define ACT_IDX 0x03C0
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#define ACT_ADDRESS_R 0x03C0
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#define ACT_DATA 0x03C0
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#define ACT_ADDRESS_RESET 0x03DA
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#define ACT_PALETTE0 0x00
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#define ACT_PALETTE1 0x01
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#define ACT_PALETTE2 0x02
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#define ACT_PALETTE3 0x03
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#define ACT_PALETTE4 0x04
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#define ACT_PALETTE5 0x05
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#define ACT_PALETTE6 0x06
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#define ACT_PALETTE7 0x07
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#define ACT_PALETTE8 0x08
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#define ACT_PALETTE9 0x09
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#define ACT_PALETTE10 0x0A
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#define ACT_PALETTE11 0x0B
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#define ACT_PALETTE12 0x0C
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#define ACT_PALETTE13 0x0D
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#define ACT_PALETTE14 0x0E
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#define ACT_PALETTE15 0x0F
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#define ACT_ATTR_MODE_CNTL 0x10
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#define ACT_OVERSCAN_COLOR 0x11
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#define ACT_COLOR_PLANE_ENA 0x12
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#define ACT_HOR_PEL_PANNING 0x13
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#define ACT_COLOR_SELECT 0x14
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/*
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* PLL
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*/
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#define PLL_IDX 0x83c8
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#define PLL_DATA 0x83c9
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/*
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* Blitter operations
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*/
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#define Z3BLTclear 0x00 /* 0 */
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#define Z3BLTand 0x80 /* src AND dst */
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#define Z3BLTandReverse 0x40 /* src AND NOT dst */
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#define Z3BLTcopy 0xc0 /* src */
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#define Z3BLTandInverted 0x20 /* NOT src AND dst */
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#define Z3BLTnoop 0xa0 /* dst */
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#define Z3BLTxor 0x60 /* src XOR dst */
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#define Z3BLTor 0xe0 /* src OR dst */
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#define Z3BLTnor 0x10 /* NOT src AND NOT dst */
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#define Z3BLTequiv 0x90 /* NOT src XOR dst */
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#define Z3BLTinvert 0x50 /* NOT dst */
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#define Z3BLTorReverse 0xd0 /* src OR NOT dst */
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#define Z3BLTcopyInverted 0x30 /* NOT src */
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#define Z3BLTorInverted 0xb0 /* NOT src OR dst */
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#define Z3BLTnand 0x70 /* NOT src OR NOT dst */
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#define Z3BLTset 0xf0 /* 1 */
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