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b9c7eb498d
__ipipe_{stall, unstall}_root_raw() identifiers may leave the reader
under the impression that only the virtual state is affected by these
operations, which is wrong. Pick names following the convention used
throughout the interrupt pipeline code.
Signed-off-by: Philippe Gerum <rpm@xenomai.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
250 lines
6.9 KiB
C
250 lines
6.9 KiB
C
/* -*- linux-c -*-
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* include/asm-blackfin/ipipe.h
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*
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* Copyright (C) 2002-2007 Philippe Gerum.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139,
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* USA; either version 2 of the License, or (at your option) any later
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* version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef __ASM_BLACKFIN_IPIPE_H
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#define __ASM_BLACKFIN_IPIPE_H
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#ifdef CONFIG_IPIPE
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#include <linux/cpumask.h>
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#include <linux/list.h>
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#include <linux/threads.h>
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#include <linux/irq.h>
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#include <linux/ipipe_percpu.h>
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#include <asm/ptrace.h>
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#include <asm/irq.h>
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#include <asm/bitops.h>
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#include <asm/atomic.h>
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#include <asm/traps.h>
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#define IPIPE_ARCH_STRING "1.11-00"
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#define IPIPE_MAJOR_NUMBER 1
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#define IPIPE_MINOR_NUMBER 11
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#define IPIPE_PATCH_NUMBER 0
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#ifdef CONFIG_SMP
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#error "I-pipe/blackfin: SMP not implemented"
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#else /* !CONFIG_SMP */
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#define ipipe_processor_id() 0
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#endif /* CONFIG_SMP */
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#define prepare_arch_switch(next) \
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do { \
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ipipe_schedule_notify(current, next); \
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local_irq_disable_hw(); \
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} while (0)
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#define task_hijacked(p) \
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({ \
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int __x__ = __ipipe_root_domain_p; \
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__clear_bit(IPIPE_SYNC_FLAG, &ipipe_root_cpudom_var(status)); \
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if (__x__) \
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local_irq_enable_hw(); \
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!__x__; \
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})
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struct ipipe_domain;
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struct ipipe_sysinfo {
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int ncpus; /* Number of CPUs on board */
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u64 cpufreq; /* CPU frequency (in Hz) */
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/* Arch-dependent block */
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struct {
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unsigned tmirq; /* Timer tick IRQ */
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u64 tmfreq; /* Timer frequency */
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} archdep;
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};
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#define ipipe_read_tsc(t) \
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({ \
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unsigned long __cy2; \
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__asm__ __volatile__ ("1: %0 = CYCLES2\n" \
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"%1 = CYCLES\n" \
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"%2 = CYCLES2\n" \
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"CC = %2 == %0\n" \
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"if ! CC jump 1b\n" \
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: "=d,a" (((unsigned long *)&t)[1]), \
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"=d,a" (((unsigned long *)&t)[0]), \
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"=d,a" (__cy2) \
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: /*no input*/ : "CC"); \
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t; \
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})
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#define ipipe_cpu_freq() __ipipe_core_clock
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#define ipipe_tsc2ns(_t) (((unsigned long)(_t)) * __ipipe_freq_scale)
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#define ipipe_tsc2us(_t) (ipipe_tsc2ns(_t) / 1000 + 1)
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/* Private interface -- Internal use only */
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#define __ipipe_check_platform() do { } while (0)
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#define __ipipe_init_platform() do { } while (0)
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extern atomic_t __ipipe_irq_lvdepth[IVG15 + 1];
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extern unsigned long __ipipe_irq_lvmask;
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extern struct ipipe_domain ipipe_root;
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/* enable/disable_irqdesc _must_ be used in pairs. */
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void __ipipe_enable_irqdesc(struct ipipe_domain *ipd,
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unsigned irq);
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void __ipipe_disable_irqdesc(struct ipipe_domain *ipd,
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unsigned irq);
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#define __ipipe_enable_irq(irq) (irq_desc[irq].chip->unmask(irq))
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#define __ipipe_disable_irq(irq) (irq_desc[irq].chip->mask(irq))
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static inline int __ipipe_check_tickdev(const char *devname)
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{
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return 1;
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}
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static inline void __ipipe_lock_root(void)
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{
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set_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status));
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}
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static inline void __ipipe_unlock_root(void)
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{
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clear_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status));
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}
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void __ipipe_enable_pipeline(void);
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#define __ipipe_hook_critical_ipi(ipd) do { } while (0)
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#define __ipipe_sync_pipeline ___ipipe_sync_pipeline
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void ___ipipe_sync_pipeline(unsigned long syncmask);
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void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs);
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int __ipipe_get_irq_priority(unsigned irq);
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void __ipipe_serial_debug(const char *fmt, ...);
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asmlinkage void __ipipe_call_irqtail(unsigned long addr);
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DECLARE_PER_CPU(struct pt_regs, __ipipe_tick_regs);
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extern unsigned long __ipipe_core_clock;
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extern unsigned long __ipipe_freq_scale;
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extern unsigned long __ipipe_irq_tail_hook;
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static inline unsigned long __ipipe_ffnz(unsigned long ul)
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{
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return ffs(ul) - 1;
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}
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#define __ipipe_run_irqtail() /* Must be a macro */ \
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do { \
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unsigned long __pending; \
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CSYNC(); \
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__pending = bfin_read_IPEND(); \
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if (__pending & 0x8000) { \
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__pending &= ~0x8010; \
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if (__pending && (__pending & (__pending - 1)) == 0) \
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__ipipe_call_irqtail(__ipipe_irq_tail_hook); \
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} \
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} while (0)
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#define __ipipe_run_isr(ipd, irq) \
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do { \
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if (!__ipipe_pipeline_head_p(ipd)) \
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local_irq_enable_hw(); \
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if (ipd == ipipe_root_domain) { \
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if (unlikely(ipipe_virtual_irq_p(irq))) { \
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irq_enter(); \
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ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \
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irq_exit(); \
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} else \
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ipd->irqs[irq].handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs)); \
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} else { \
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__clear_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \
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ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \
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/* Attempt to exit the outer interrupt level before \
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* starting the deferred IRQ processing. */ \
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__ipipe_run_irqtail(); \
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__set_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \
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} \
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local_irq_disable_hw(); \
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} while (0)
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#define __ipipe_syscall_watched_p(p, sc) \
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(((p)->flags & PF_EVNOTIFY) || (unsigned long)sc >= NR_syscalls)
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void ipipe_init_irq_threads(void);
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int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc);
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#ifdef CONFIG_TICKSOURCE_CORETMR
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#define IRQ_SYSTMR IRQ_CORETMR
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#define IRQ_PRIOTMR IRQ_CORETMR
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#else
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#define IRQ_SYSTMR IRQ_TIMER0
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#define IRQ_PRIOTMR CONFIG_IRQ_TIMER0
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#endif
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#ifdef CONFIG_BF561
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#define bfin_write_TIMER_DISABLE(val) bfin_write_TMRS8_DISABLE(val)
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#define bfin_write_TIMER_ENABLE(val) bfin_write_TMRS8_ENABLE(val)
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#define bfin_write_TIMER_STATUS(val) bfin_write_TMRS8_STATUS(val)
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#define bfin_read_TIMER_STATUS() bfin_read_TMRS8_STATUS()
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#elif defined(CONFIG_BF54x)
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#define bfin_write_TIMER_DISABLE(val) bfin_write_TIMER_DISABLE0(val)
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#define bfin_write_TIMER_ENABLE(val) bfin_write_TIMER_ENABLE0(val)
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#define bfin_write_TIMER_STATUS(val) bfin_write_TIMER_STATUS0(val)
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#define bfin_read_TIMER_STATUS(val) bfin_read_TIMER_STATUS0(val)
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#endif
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#define __ipipe_root_tick_p(regs) ((regs->ipend & 0x10) != 0)
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#else /* !CONFIG_IPIPE */
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#define task_hijacked(p) 0
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#define ipipe_trap_notify(t, r) 0
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#define ipipe_init_irq_threads() do { } while (0)
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#define ipipe_start_irq_thread(irq, desc) 0
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#ifndef CONFIG_TICKSOURCE_GPTMR0
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#define IRQ_SYSTMR IRQ_CORETMR
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#define IRQ_PRIOTMR IRQ_CORETMR
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#else
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#define IRQ_SYSTMR IRQ_TIMER0
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#define IRQ_PRIOTMR CONFIG_IRQ_TIMER0
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#endif
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#define __ipipe_root_tick_p(regs) 1
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#endif /* !CONFIG_IPIPE */
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#define ipipe_update_tick_evtdev(evtdev) do { } while (0)
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#endif /* !__ASM_BLACKFIN_IPIPE_H */
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