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ca6ffc64cb
Also cleanup register specific to RS400/RS480. This patch also fix legacy VGA register used to disable VGA access we were programming wrong register. Now we should properly disable VGA on r100 up to rs400 asics. Note that RS400/RS480 resume is broken, it hangs the computer while reprogramming dynamic clock, doesn't work either without that patch. We need to spend more time investigating this issue. Version 2 of the patch remove dead code that was left commented out in the previous version. Version 3 correct the placement on IGP of the VRAM inside GPU address space to match the stollen RAM placement of IGP. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
52 lines
2.7 KiB
C
52 lines
2.7 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#ifndef __RV350D_H__
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#define __RV350D_H__
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/* RV350, RV380 registers */
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/* #define R_00000D_SCLK_CNTL 0x00000D */
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#define S_00000D_FORCE_VAP(x) (((x) & 0x1) << 21)
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#define G_00000D_FORCE_VAP(x) (((x) >> 21) & 0x1)
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#define C_00000D_FORCE_VAP 0xFFDFFFFF
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#define S_00000D_FORCE_SR(x) (((x) & 0x1) << 25)
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#define G_00000D_FORCE_SR(x) (((x) >> 25) & 0x1)
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#define C_00000D_FORCE_SR 0xFDFFFFFF
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#define S_00000D_FORCE_PX(x) (((x) & 0x1) << 26)
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#define G_00000D_FORCE_PX(x) (((x) >> 26) & 0x1)
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#define C_00000D_FORCE_PX 0xFBFFFFFF
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#define S_00000D_FORCE_TX(x) (((x) & 0x1) << 27)
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#define G_00000D_FORCE_TX(x) (((x) >> 27) & 0x1)
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#define C_00000D_FORCE_TX 0xF7FFFFFF
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#define S_00000D_FORCE_US(x) (((x) & 0x1) << 28)
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#define G_00000D_FORCE_US(x) (((x) >> 28) & 0x1)
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#define C_00000D_FORCE_US 0xEFFFFFFF
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#define S_00000D_FORCE_SU(x) (((x) & 0x1) << 30)
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#define G_00000D_FORCE_SU(x) (((x) >> 30) & 0x1)
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#define C_00000D_FORCE_SU 0xBFFFFFFF
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#endif
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