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a3a0f8c8ed
Add the Cisco Powertv cable settop box to the MIPS tree. This platform is based on a MIPS 24Kc processor with various devices integrated on the same ASIC. There are multiple models of this box, with differing configuration but the same kernel runs across the product line. Signed-off-by: David VomLehn <dvomlehn@cisco.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/132/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
98 lines
2.7 KiB
C
98 lines
2.7 KiB
C
/*
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* Locations of devices in the Cronus ASIC
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*
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* Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* Author: Ken Eppinett
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* David Schleef <ds@schleef.org>
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*
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* Description: Defines the platform resources for the SA settop.
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*/
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#include <asm/mach-powertv/asic.h>
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const struct register_map cronus_register_map = {
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.eic_slow0_strt_add = 0x000000,
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.eic_cfg_bits = 0x000038,
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.eic_ready_status = 0x00004C,
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.chipver3 = 0x2A0800,
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.chipver2 = 0x2A0804,
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.chipver1 = 0x2A0808,
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.chipver0 = 0x2A080C,
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/* The registers of IRBlaster */
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.uart1_intstat = 0x2A1800,
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.uart1_inten = 0x2A1804,
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.uart1_config1 = 0x2A1808,
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.uart1_config2 = 0x2A180C,
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.uart1_divisorhi = 0x2A1810,
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.uart1_divisorlo = 0x2A1814,
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.uart1_data = 0x2A1818,
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.uart1_status = 0x2A181C,
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.int_stat_3 = 0x2A2800,
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.int_stat_2 = 0x2A2804,
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.int_stat_1 = 0x2A2808,
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.int_stat_0 = 0x2A280C,
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.int_config = 0x2A2810,
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.int_int_scan = 0x2A2818,
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.ien_int_3 = 0x2A2830,
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.ien_int_2 = 0x2A2834,
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.ien_int_1 = 0x2A2838,
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.ien_int_0 = 0x2A283C,
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.int_level_3_3 = 0x2A2880,
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.int_level_3_2 = 0x2A2884,
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.int_level_3_1 = 0x2A2888,
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.int_level_3_0 = 0x2A288C,
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.int_level_2_3 = 0x2A2890,
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.int_level_2_2 = 0x2A2894,
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.int_level_2_1 = 0x2A2898,
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.int_level_2_0 = 0x2A289C,
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.int_level_1_3 = 0x2A28A0,
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.int_level_1_2 = 0x2A28A4,
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.int_level_1_1 = 0x2A28A8,
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.int_level_1_0 = 0x2A28AC,
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.int_level_0_3 = 0x2A28B0,
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.int_level_0_2 = 0x2A28B4,
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.int_level_0_1 = 0x2A28B8,
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.int_level_0_0 = 0x2A28BC,
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.int_docsis_en = 0x2A28F4,
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.mips_pll_setup = 0x1C0000,
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.usb_fs = 0x1C0018,
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.test_bus = 0x1C00CC,
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.crt_spare = 0x1c00d4,
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.usb2_ohci_int_mask = 0x20000C,
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.usb2_strap = 0x200014,
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.ehci_hcapbase = 0x21FE00,
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.ohci_hc_revision = 0x1E0000,
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.bcm1_bs_lmi_steer = 0x2E0008,
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.usb2_control = 0x2E004C,
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.usb2_stbus_obc = 0x21FF00,
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.usb2_stbus_mess_size = 0x21FF04,
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.usb2_stbus_chunk_size = 0x21FF08,
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.pcie_regs = 0x220000,
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.tim_ch = 0x2A2C10,
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.tim_cl = 0x2A2C14,
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.gpio_dout = 0x2A2C20,
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.gpio_din = 0x2A2C24,
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.gpio_dir = 0x2A2C2C,
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.watchdog = 0x2A2C30,
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.front_panel = 0x2A3800,
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};
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