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7bbd827750
This patch hacks the current PowerMac Alsa driver to add some basic support of analog sound output to some desktop G5s. It has severe limitations though: - Only 44100Khz 16 bits - Only work on G5 models using a TAS3004 analog code, that is early single CPU desktops and all dual CPU desktops at this date, but none of the more recent ones like iMac G5. - It does analog only, no digital/SPDIF support at all, no native AC3 support Better support would require a complete rewrite of the driver (which I am working on, but don't hold your breath), to properly support the diversity of apple sound HW setup, including dual codecs, several i2s busses, all the new codecs used in the new machines, proper clock switching with digital, etc etc etc... This patch applies on top of the other PowerMac sound patches I posted in the past couple of days (new powerbook support and sleep fixes). Note: This is a FAQ entry for PowerMac sound support with TI codecs: They have a feature called "DRC" which is automatically enabled for the internal speaker (at least when auto mute control is enabled) which will cause your sound to fade out to nothing after half a second of playback if you don't set a proper "DRC Range" in the mixer. So if you have a problem like that, check alsamixer and raise your DRC Range to something reasonable. Note2: This patch will also add auto-mute of the speaker when line-out jack is used on some earlier desktop G4s (and on the G5) in addition to the headphone jack. If that behaviour isn't what you want, just disable auto-muting and use the manual mute controls in alsamixer. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
102 lines
3.6 KiB
C
102 lines
3.6 KiB
C
/*
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* Definitions for using the Apple Descriptor-Based DMA controller
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* in Power Macintosh computers.
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*
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* Copyright (C) 1996 Paul Mackerras.
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*/
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#ifdef __KERNEL__
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#ifndef _ASM_DBDMA_H_
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#define _ASM_DBDMA_H_
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/*
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* DBDMA control/status registers. All little-endian.
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*/
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struct dbdma_regs {
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unsigned int control; /* lets you change bits in status */
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unsigned int status; /* DMA and device status bits (see below) */
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unsigned int cmdptr_hi; /* upper 32 bits of command address */
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unsigned int cmdptr; /* (lower 32 bits of) command address (phys) */
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unsigned int intr_sel; /* select interrupt condition bit */
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unsigned int br_sel; /* select branch condition bit */
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unsigned int wait_sel; /* select wait condition bit */
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unsigned int xfer_mode;
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unsigned int data2ptr_hi;
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unsigned int data2ptr;
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unsigned int res1;
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unsigned int address_hi;
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unsigned int br_addr_hi;
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unsigned int res2[3];
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};
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/* Bits in control and status registers */
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#define RUN 0x8000
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#define PAUSE 0x4000
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#define FLUSH 0x2000
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#define WAKE 0x1000
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#define DEAD 0x0800
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#define ACTIVE 0x0400
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#define BT 0x0100
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#define DEVSTAT 0x00ff
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/*
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* DBDMA command structure. These fields are all little-endian!
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*/
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struct dbdma_cmd {
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unsigned short req_count; /* requested byte transfer count */
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unsigned short command; /* command word (has bit-fields) */
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unsigned int phy_addr; /* physical data address */
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unsigned int cmd_dep; /* command-dependent field */
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unsigned short res_count; /* residual count after completion */
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unsigned short xfer_status; /* transfer status */
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};
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/* DBDMA command values in command field */
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#define OUTPUT_MORE 0 /* transfer memory data to stream */
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#define OUTPUT_LAST 0x1000 /* ditto followed by end marker */
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#define INPUT_MORE 0x2000 /* transfer stream data to memory */
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#define INPUT_LAST 0x3000 /* ditto, expect end marker */
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#define STORE_WORD 0x4000 /* write word (4 bytes) to device reg */
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#define LOAD_WORD 0x5000 /* read word (4 bytes) from device reg */
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#define DBDMA_NOP 0x6000 /* do nothing */
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#define DBDMA_STOP 0x7000 /* suspend processing */
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/* Key values in command field */
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#define KEY_STREAM0 0 /* usual data stream */
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#define KEY_STREAM1 0x100 /* control/status stream */
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#define KEY_STREAM2 0x200 /* device-dependent stream */
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#define KEY_STREAM3 0x300 /* device-dependent stream */
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#define KEY_REGS 0x500 /* device register space */
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#define KEY_SYSTEM 0x600 /* system memory-mapped space */
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#define KEY_DEVICE 0x700 /* device memory-mapped space */
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/* Interrupt control values in command field */
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#define INTR_NEVER 0 /* don't interrupt */
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#define INTR_IFSET 0x10 /* intr if condition bit is 1 */
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#define INTR_IFCLR 0x20 /* intr if condition bit is 0 */
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#define INTR_ALWAYS 0x30 /* always interrupt */
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/* Branch control values in command field */
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#define BR_NEVER 0 /* don't branch */
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#define BR_IFSET 0x4 /* branch if condition bit is 1 */
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#define BR_IFCLR 0x8 /* branch if condition bit is 0 */
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#define BR_ALWAYS 0xc /* always branch */
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/* Wait control values in command field */
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#define WAIT_NEVER 0 /* don't wait */
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#define WAIT_IFSET 1 /* wait if condition bit is 1 */
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#define WAIT_IFCLR 2 /* wait if condition bit is 0 */
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#define WAIT_ALWAYS 3 /* always wait */
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/* Align an address for a DBDMA command structure */
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#define DBDMA_ALIGN(x) (((unsigned long)(x) + sizeof(struct dbdma_cmd) - 1) \
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& -sizeof(struct dbdma_cmd))
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/* Useful macros */
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#define DBDMA_DO_STOP(regs) do { \
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out_le32(&((regs)->control), (RUN|FLUSH)<<16); \
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while(in_le32(&((regs)->status)) & (ACTIVE|FLUSH)) \
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; \
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} while(0)
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#endif /* _ASM_DBDMA_H_ */
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#endif /* __KERNEL__ */
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