mirror of
https://github.com/adulau/aha.git
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1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
214 lines
4.1 KiB
C
214 lines
4.1 KiB
C
/*
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* PowerPC atomic operations
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*/
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#ifndef _ASM_PPC_ATOMIC_H_
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#define _ASM_PPC_ATOMIC_H_
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typedef struct { volatile int counter; } atomic_t;
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#ifdef __KERNEL__
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#define ATOMIC_INIT(i) { (i) }
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#define atomic_read(v) ((v)->counter)
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#define atomic_set(v,i) (((v)->counter) = (i))
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extern void atomic_clear_mask(unsigned long mask, unsigned long *addr);
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#ifdef CONFIG_SMP
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#define SMP_SYNC "sync"
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#define SMP_ISYNC "\n\tisync"
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#else
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#define SMP_SYNC ""
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#define SMP_ISYNC
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#endif
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/* Erratum #77 on the 405 means we need a sync or dcbt before every stwcx.
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* The old ATOMIC_SYNC_FIX covered some but not all of this.
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*/
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#ifdef CONFIG_IBM405_ERR77
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#define PPC405_ERR77(ra,rb) "dcbt " #ra "," #rb ";"
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#else
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#define PPC405_ERR77(ra,rb)
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#endif
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static __inline__ void atomic_add(int a, atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%3 # atomic_add\n\
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add %0,%2,%0\n"
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PPC405_ERR77(0,%3)
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" stwcx. %0,0,%3 \n\
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bne- 1b"
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: "=&r" (t), "=m" (v->counter)
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: "r" (a), "r" (&v->counter), "m" (v->counter)
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: "cc");
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}
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static __inline__ int atomic_add_return(int a, atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%2 # atomic_add_return\n\
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add %0,%1,%0\n"
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PPC405_ERR77(0,%2)
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" stwcx. %0,0,%2 \n\
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bne- 1b"
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SMP_ISYNC
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: "=&r" (t)
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: "r" (a), "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
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static __inline__ void atomic_sub(int a, atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%3 # atomic_sub\n\
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subf %0,%2,%0\n"
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PPC405_ERR77(0,%3)
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" stwcx. %0,0,%3 \n\
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bne- 1b"
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: "=&r" (t), "=m" (v->counter)
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: "r" (a), "r" (&v->counter), "m" (v->counter)
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: "cc");
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}
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static __inline__ int atomic_sub_return(int a, atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%2 # atomic_sub_return\n\
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subf %0,%1,%0\n"
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PPC405_ERR77(0,%2)
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" stwcx. %0,0,%2 \n\
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bne- 1b"
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SMP_ISYNC
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: "=&r" (t)
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: "r" (a), "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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static __inline__ void atomic_inc(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%2 # atomic_inc\n\
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addic %0,%0,1\n"
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PPC405_ERR77(0,%2)
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" stwcx. %0,0,%2 \n\
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bne- 1b"
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: "=&r" (t), "=m" (v->counter)
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: "r" (&v->counter), "m" (v->counter)
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: "cc");
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}
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static __inline__ int atomic_inc_return(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%1 # atomic_inc_return\n\
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addic %0,%0,1\n"
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PPC405_ERR77(0,%1)
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" stwcx. %0,0,%1 \n\
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bne- 1b"
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SMP_ISYNC
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: "=&r" (t)
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: "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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/*
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* atomic_inc_and_test - increment and test
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* @v: pointer of type atomic_t
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*
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* Atomically increments @v by 1
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* and returns true if the result is zero, or false for all
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* other cases.
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*/
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#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
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static __inline__ void atomic_dec(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%2 # atomic_dec\n\
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addic %0,%0,-1\n"
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PPC405_ERR77(0,%2)\
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" stwcx. %0,0,%2\n\
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bne- 1b"
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: "=&r" (t), "=m" (v->counter)
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: "r" (&v->counter), "m" (v->counter)
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: "cc");
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}
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static __inline__ int atomic_dec_return(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%1 # atomic_dec_return\n\
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addic %0,%0,-1\n"
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PPC405_ERR77(0,%1)
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" stwcx. %0,0,%1\n\
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bne- 1b"
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SMP_ISYNC
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: "=&r" (t)
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: "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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#define atomic_sub_and_test(a, v) (atomic_sub_return((a), (v)) == 0)
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#define atomic_dec_and_test(v) (atomic_dec_return((v)) == 0)
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/*
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* Atomically test *v and decrement if it is greater than 0.
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* The function returns the old value of *v minus 1.
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*/
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static __inline__ int atomic_dec_if_positive(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%1 # atomic_dec_if_positive\n\
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addic. %0,%0,-1\n\
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blt- 2f\n"
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PPC405_ERR77(0,%1)
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" stwcx. %0,0,%1\n\
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bne- 1b"
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SMP_ISYNC
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"\n\
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2:" : "=&r" (t)
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: "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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#define __MB __asm__ __volatile__ (SMP_SYNC : : : "memory")
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#define smp_mb__before_atomic_dec() __MB
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#define smp_mb__after_atomic_dec() __MB
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#define smp_mb__before_atomic_inc() __MB
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#define smp_mb__after_atomic_inc() __MB
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#endif /* __KERNEL__ */
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#endif /* _ASM_PPC_ATOMIC_H_ */
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