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1c8d7b0a56
Add the new API pci_enable_msi_block() to allow drivers to request multiple MSI and reimplement pci_enable_msi in terms of pci_enable_msi_block. Ensure that the architecture back ends don't have to know about multiple MSI. Signed-off-by: Matthew Wilcox <willy@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
56 lines
1.6 KiB
C
56 lines
1.6 KiB
C
#ifndef LINUX_MSI_H
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#define LINUX_MSI_H
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#include <linux/list.h>
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struct msi_msg {
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u32 address_lo; /* low 32 bits of msi message address */
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u32 address_hi; /* high 32 bits of msi message address */
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u32 data; /* 16 bits of msi message data */
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};
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/* Helper functions */
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struct irq_desc;
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extern void mask_msi_irq(unsigned int irq);
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extern void unmask_msi_irq(unsigned int irq);
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extern void read_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg);
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extern void write_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg);
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extern void read_msi_msg(unsigned int irq, struct msi_msg *msg);
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extern void write_msi_msg(unsigned int irq, struct msi_msg *msg);
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struct msi_desc {
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struct {
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__u8 is_msix : 1;
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__u8 multiple: 3; /* log2 number of messages */
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__u8 maskbit : 1; /* mask-pending bit supported ? */
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__u8 is_64 : 1; /* Address size: 0=32bit 1=64bit */
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__u8 pos; /* Location of the msi capability */
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__u16 entry_nr; /* specific enabled entry */
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unsigned default_irq; /* default pre-assigned irq */
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} msi_attrib;
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u32 masked; /* mask bits */
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unsigned int irq;
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struct list_head list;
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union {
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void __iomem *mask_base;
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u8 mask_pos;
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};
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struct pci_dev *dev;
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/* Last set MSI message */
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struct msi_msg msg;
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};
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/*
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* The arch hook for setup up msi irqs
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*/
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int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc);
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void arch_teardown_msi_irq(unsigned int irq);
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extern int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type);
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extern void arch_teardown_msi_irqs(struct pci_dev *dev);
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extern int arch_msi_check_device(struct pci_dev* dev, int nvec, int type);
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#endif /* LINUX_MSI_H */
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