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Virtually index, physically tagged cache architectures can get away without cache flushing when forking. This patch adds a new cache flushing function flush_cache_dup_mm(struct mm_struct *) which for the moment I've implemented to do the same thing on all architectures except on MIPS where it's a no-op. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
53 lines
2 KiB
C
53 lines
2 KiB
C
/*
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* linux/include/asm-arm/cacheflush.h
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*
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* Copyright (C) 2000-2002 Russell King
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* Copyright (C) 2003 Ian Molton
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* ARM26 cache 'functions'
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*
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*/
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#ifndef _ASMARM_CACHEFLUSH_H
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#define _ASMARM_CACHEFLUSH_H
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#if 1 //FIXME - BAD INCLUDES!!!
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#include <linux/sched.h>
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#include <linux/mm.h>
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#endif
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#define flush_cache_all() do { } while (0)
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#define flush_cache_mm(mm) do { } while (0)
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#define flush_cache_dup_mm(mm) do { } while (0)
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#define flush_cache_range(vma,start,end) do { } while (0)
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#define flush_cache_page(vma,vmaddr,pfn) do { } while (0)
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#define flush_cache_vmap(start, end) do { } while (0)
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#define flush_cache_vunmap(start, end) do { } while (0)
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#define invalidate_dcache_range(start,end) do { } while (0)
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#define clean_dcache_range(start,end) do { } while (0)
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#define flush_dcache_range(start,end) do { } while (0)
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#define flush_dcache_page(page) do { } while (0)
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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#define clean_dcache_entry(_s) do { } while (0)
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#define clean_cache_entry(_start) do { } while (0)
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#define flush_icache_user_range(start,end, bob, fred) do { } while (0)
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#define flush_icache_range(start,end) do { } while (0)
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#define flush_icache_page(vma,page) do { } while (0)
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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memcpy(dst, src, len)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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memcpy(dst, src, len)
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/* DAG: ARM3 will flush cache on MEMC updates anyway? so don't bother */
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/* IM : Yes, it will, but only if setup to do so (we do this). */
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#define clean_cache_area(_start,_size) do { } while (0)
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#endif
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