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4fb2847437
Instruction fault status register, IFSR, was introduced on ARMv6 to
provide status information about the last insturction fault. It
needed for proper prefetch abort handling.
Now we have three prefetch abort model:
* legacy - for CPUs before ARMv6. They doesn't provide neither
IFSR nor IFAR. We simulate IFSR with section translation fault
status for them to generalize code;
* ARMv6 - provides IFSR, but not IFAR;
* ARMv7 - provides both IFSR and IFAR.
Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
423 lines
11 KiB
ArmAsm
423 lines
11 KiB
ArmAsm
/*
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* linux/arch/arm/mm/proc-arm6,7.S
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*
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* Copyright (C) 1997-2000 Russell King
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* hacked for non-paged-MM by Hyok S. Choi, 2003.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* These are the low level assembler for performing cache and TLB
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* functions on the ARM610 & ARM710.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/hwcap.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include <asm/ptrace.h>
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#include "proc-macros.S"
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ENTRY(cpu_arm6_dcache_clean_area)
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ENTRY(cpu_arm7_dcache_clean_area)
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mov pc, lr
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/*
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* Function: arm6_7_data_abort ()
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*
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* Params : r2 = address of aborted instruction
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* : sp = pointer to registers
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*
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* Purpose : obtain information about current aborted instruction
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*
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* Returns : r0 = address of abort
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* : r1 = FSR
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*/
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ENTRY(cpu_arm7_data_abort)
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mrc p15, 0, r1, c5, c0, 0 @ get FSR
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mrc p15, 0, r0, c6, c0, 0 @ get FAR
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ldr r8, [r0] @ read arm instruction
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tst r8, #1 << 20 @ L = 0 -> write?
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orreq r1, r1, #1 << 11 @ yes.
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and r7, r8, #15 << 24
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add pc, pc, r7, lsr #22 @ Now branch to the relevant processing routine
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nop
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/* 0 */ b .data_unknown
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/* 1 */ mov pc, lr @ swp
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/* 2 */ b .data_unknown
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/* 3 */ b .data_unknown
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/* 4 */ b .data_arm_lateldrpostconst @ ldr rd, [rn], #m
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/* 5 */ b .data_arm_lateldrpreconst @ ldr rd, [rn, #m]
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/* 6 */ b .data_arm_lateldrpostreg @ ldr rd, [rn], rm
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/* 7 */ b .data_arm_lateldrprereg @ ldr rd, [rn, rm]
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/* 8 */ b .data_arm_ldmstm @ ldm*a rn, <rlist>
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/* 9 */ b .data_arm_ldmstm @ ldm*b rn, <rlist>
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/* a */ b .data_unknown
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/* b */ b .data_unknown
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/* c */ mov pc, lr @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m
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/* d */ mov pc, lr @ ldc rd, [rn, #m]
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/* e */ b .data_unknown
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/* f */
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.data_unknown: @ Part of jumptable
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mov r0, r2
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mov r1, r8
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mov r2, sp
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bl baddataabort
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b ret_from_exception
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ENTRY(cpu_arm6_data_abort)
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mrc p15, 0, r1, c5, c0, 0 @ get FSR
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mrc p15, 0, r0, c6, c0, 0 @ get FAR
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ldr r8, [r2] @ read arm instruction
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tst r8, #1 << 20 @ L = 0 -> write?
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orreq r1, r1, #1 << 11 @ yes.
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and r7, r8, #14 << 24
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teq r7, #8 << 24 @ was it ldm/stm
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movne pc, lr
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.data_arm_ldmstm:
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tst r8, #1 << 21 @ check writeback bit
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moveq pc, lr @ no writeback -> no fixup
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mov r7, #0x11
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orr r7, r7, #0x1100
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and r6, r8, r7
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and r2, r8, r7, lsl #1
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add r6, r6, r2, lsr #1
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and r2, r8, r7, lsl #2
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add r6, r6, r2, lsr #2
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and r2, r8, r7, lsl #3
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add r6, r6, r2, lsr #3
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add r6, r6, r6, lsr #8
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add r6, r6, r6, lsr #4
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and r6, r6, #15 @ r6 = no. of registers to transfer.
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and r5, r8, #15 << 16 @ Extract 'n' from instruction
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ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
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tst r8, #1 << 23 @ Check U bit
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subne r7, r7, r6, lsl #2 @ Undo increment
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addeq r7, r7, r6, lsl #2 @ Undo decrement
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str r7, [sp, r5, lsr #14] @ Put register 'Rn'
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mov pc, lr
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.data_arm_apply_r6_and_rn:
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and r5, r8, #15 << 16 @ Extract 'n' from instruction
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ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
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tst r8, #1 << 23 @ Check U bit
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subne r7, r7, r6 @ Undo incrmenet
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addeq r7, r7, r6 @ Undo decrement
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str r7, [sp, r5, lsr #14] @ Put register 'Rn'
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mov pc, lr
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.data_arm_lateldrpreconst:
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tst r8, #1 << 21 @ check writeback bit
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moveq pc, lr @ no writeback -> no fixup
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.data_arm_lateldrpostconst:
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movs r2, r8, lsl #20 @ Get offset
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moveq pc, lr @ zero -> no fixup
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and r5, r8, #15 << 16 @ Extract 'n' from instruction
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ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
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tst r8, #1 << 23 @ Check U bit
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subne r7, r7, r2, lsr #20 @ Undo increment
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addeq r7, r7, r2, lsr #20 @ Undo decrement
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str r7, [sp, r5, lsr #14] @ Put register 'Rn'
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mov pc, lr
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.data_arm_lateldrprereg:
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tst r8, #1 << 21 @ check writeback bit
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moveq pc, lr @ no writeback -> no fixup
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.data_arm_lateldrpostreg:
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and r7, r8, #15 @ Extract 'm' from instruction
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ldr r6, [sp, r7, lsl #2] @ Get register 'Rm'
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mov r5, r8, lsr #7 @ get shift count
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ands r5, r5, #31
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and r7, r8, #0x70 @ get shift type
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orreq r7, r7, #8 @ shift count = 0
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add pc, pc, r7
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nop
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mov r6, r6, lsl r5 @ 0: LSL #!0
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b .data_arm_apply_r6_and_rn
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b .data_arm_apply_r6_and_rn @ 1: LSL #0
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nop
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b .data_unknown @ 2: MUL?
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nop
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b .data_unknown @ 3: MUL?
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nop
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mov r6, r6, lsr r5 @ 4: LSR #!0
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b .data_arm_apply_r6_and_rn
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mov r6, r6, lsr #32 @ 5: LSR #32
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b .data_arm_apply_r6_and_rn
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b .data_unknown @ 6: MUL?
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nop
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b .data_unknown @ 7: MUL?
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nop
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mov r6, r6, asr r5 @ 8: ASR #!0
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b .data_arm_apply_r6_and_rn
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mov r6, r6, asr #32 @ 9: ASR #32
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b .data_arm_apply_r6_and_rn
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b .data_unknown @ A: MUL?
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nop
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b .data_unknown @ B: MUL?
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nop
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mov r6, r6, ror r5 @ C: ROR #!0
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b .data_arm_apply_r6_and_rn
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mov r6, r6, rrx @ D: RRX
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b .data_arm_apply_r6_and_rn
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b .data_unknown @ E: MUL?
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nop
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b .data_unknown @ F: MUL?
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/*
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* Function: arm6_7_proc_init (void)
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* : arm6_7_proc_fin (void)
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*
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* Notes : This processor does not require these
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*/
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ENTRY(cpu_arm6_proc_init)
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ENTRY(cpu_arm7_proc_init)
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mov pc, lr
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ENTRY(cpu_arm6_proc_fin)
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ENTRY(cpu_arm7_proc_fin)
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mov r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
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msr cpsr_c, r0
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mov r0, #0x31 @ ....S..DP...M
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mcr p15, 0, r0, c1, c0, 0 @ disable caches
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mov pc, lr
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ENTRY(cpu_arm6_do_idle)
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ENTRY(cpu_arm7_do_idle)
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mov pc, lr
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/*
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* Function: arm6_7_switch_mm(unsigned long pgd_phys)
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* Params : pgd_phys Physical address of page table
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* Purpose : Perform a task switch, saving the old processes state, and restoring
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* the new.
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*/
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ENTRY(cpu_arm6_switch_mm)
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ENTRY(cpu_arm7_switch_mm)
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#ifdef CONFIG_MMU
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mov r1, #0
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mcr p15, 0, r1, c7, c0, 0 @ flush cache
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mcr p15, 0, r0, c2, c0, 0 @ update page table ptr
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mcr p15, 0, r1, c5, c0, 0 @ flush TLBs
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#endif
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mov pc, lr
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/*
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* Function: arm6_7_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext)
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* Params : r0 = Address to set
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* : r1 = value to set
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* Purpose : Set a PTE and flush it out of any WB cache
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*/
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.align 5
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ENTRY(cpu_arm6_set_pte_ext)
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ENTRY(cpu_arm7_set_pte_ext)
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#ifdef CONFIG_MMU
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armv3_set_pte_ext wc_disable=0
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#endif /* CONFIG_MMU */
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mov pc, lr
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/*
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* Function: _arm6_7_reset
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* Params : r0 = address to jump to
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* Notes : This sets up everything for a reset
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*/
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ENTRY(cpu_arm6_reset)
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ENTRY(cpu_arm7_reset)
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mov r1, #0
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mcr p15, 0, r1, c7, c0, 0 @ flush cache
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#ifdef CONFIG_MMU
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mcr p15, 0, r1, c5, c0, 0 @ flush TLB
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#endif
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mov r1, #0x30
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mcr p15, 0, r1, c1, c0, 0 @ turn off MMU etc
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mov pc, r0
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__INIT
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.type __arm6_setup, #function
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__arm6_setup: mov r0, #0
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mcr p15, 0, r0, c7, c0 @ flush caches on v3
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#ifdef CONFIG_MMU
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mcr p15, 0, r0, c5, c0 @ flush TLBs on v3
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mov r0, #0x3d @ . ..RS BLDP WCAM
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orr r0, r0, #0x100 @ . ..01 0011 1101
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#else
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mov r0, #0x3c @ . ..RS BLDP WCA.
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#endif
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mov pc, lr
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.size __arm6_setup, . - __arm6_setup
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.type __arm7_setup, #function
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__arm7_setup: mov r0, #0
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mcr p15, 0, r0, c7, c0 @ flush caches on v3
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#ifdef CONFIG_MMU
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mcr p15, 0, r0, c5, c0 @ flush TLBs on v3
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mcr p15, 0, r0, c3, c0 @ load domain access register
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mov r0, #0x7d @ . ..RS BLDP WCAM
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orr r0, r0, #0x100 @ . ..01 0111 1101
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#else
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mov r0, #0x7c @ . ..RS BLDP WCA.
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#endif
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mov pc, lr
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.size __arm7_setup, . - __arm7_setup
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__INITDATA
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/*
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* Purpose : Function pointers used to access above functions - all calls
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* come through these
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*/
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.type arm6_processor_functions, #object
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ENTRY(arm6_processor_functions)
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.word cpu_arm6_data_abort
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.word legacy_pabort
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.word cpu_arm6_proc_init
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.word cpu_arm6_proc_fin
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.word cpu_arm6_reset
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.word cpu_arm6_do_idle
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.word cpu_arm6_dcache_clean_area
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.word cpu_arm6_switch_mm
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.word cpu_arm6_set_pte_ext
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.size arm6_processor_functions, . - arm6_processor_functions
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/*
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* Purpose : Function pointers used to access above functions - all calls
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* come through these
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*/
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.type arm7_processor_functions, #object
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ENTRY(arm7_processor_functions)
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.word cpu_arm7_data_abort
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.word legacy_pabort
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.word cpu_arm7_proc_init
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.word cpu_arm7_proc_fin
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.word cpu_arm7_reset
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.word cpu_arm7_do_idle
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.word cpu_arm7_dcache_clean_area
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.word cpu_arm7_switch_mm
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.word cpu_arm7_set_pte_ext
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.size arm7_processor_functions, . - arm7_processor_functions
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.section ".rodata"
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.type cpu_arch_name, #object
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cpu_arch_name: .asciz "armv3"
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.size cpu_arch_name, . - cpu_arch_name
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.type cpu_elf_name, #object
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cpu_elf_name: .asciz "v3"
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.size cpu_elf_name, . - cpu_elf_name
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.type cpu_arm6_name, #object
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cpu_arm6_name: .asciz "ARM6"
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.size cpu_arm6_name, . - cpu_arm6_name
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.type cpu_arm610_name, #object
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cpu_arm610_name:
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.asciz "ARM610"
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.size cpu_arm610_name, . - cpu_arm610_name
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.type cpu_arm7_name, #object
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cpu_arm7_name: .asciz "ARM7"
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.size cpu_arm7_name, . - cpu_arm7_name
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.type cpu_arm710_name, #object
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cpu_arm710_name:
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.asciz "ARM710"
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.size cpu_arm710_name, . - cpu_arm710_name
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.align
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.section ".proc.info.init", #alloc, #execinstr
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.type __arm6_proc_info, #object
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__arm6_proc_info:
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.long 0x41560600
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.long 0xfffffff0
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.long 0x00000c1e
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.long PMD_TYPE_SECT | \
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PMD_BIT4 | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ
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b __arm6_setup
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.long cpu_arch_name
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.long cpu_elf_name
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.long HWCAP_SWP | HWCAP_26BIT
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.long cpu_arm6_name
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.long arm6_processor_functions
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.long v3_tlb_fns
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.long v3_user_fns
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.long v3_cache_fns
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.size __arm6_proc_info, . - __arm6_proc_info
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.type __arm610_proc_info, #object
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__arm610_proc_info:
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.long 0x41560610
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.long 0xfffffff0
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.long 0x00000c1e
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.long PMD_TYPE_SECT | \
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PMD_BIT4 | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ
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b __arm6_setup
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.long cpu_arch_name
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.long cpu_elf_name
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.long HWCAP_SWP | HWCAP_26BIT
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.long cpu_arm610_name
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.long arm6_processor_functions
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.long v3_tlb_fns
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.long v3_user_fns
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.long v3_cache_fns
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.size __arm610_proc_info, . - __arm610_proc_info
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.type __arm7_proc_info, #object
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__arm7_proc_info:
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.long 0x41007000
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.long 0xffffff00
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.long 0x00000c1e
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.long PMD_TYPE_SECT | \
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PMD_BIT4 | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ
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b __arm7_setup
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.long cpu_arch_name
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.long cpu_elf_name
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.long HWCAP_SWP | HWCAP_26BIT
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.long cpu_arm7_name
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.long arm7_processor_functions
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.long v3_tlb_fns
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.long v3_user_fns
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.long v3_cache_fns
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.size __arm7_proc_info, . - __arm7_proc_info
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.type __arm710_proc_info, #object
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__arm710_proc_info:
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.long 0x41007100
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.long 0xfff8ff00
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.long PMD_TYPE_SECT | \
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PMD_SECT_BUFFERABLE | \
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PMD_SECT_CACHEABLE | \
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PMD_BIT4 | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ
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.long PMD_TYPE_SECT | \
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PMD_BIT4 | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ
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b __arm7_setup
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.long cpu_arch_name
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.long cpu_elf_name
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.long HWCAP_SWP | HWCAP_26BIT
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.long cpu_arm710_name
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.long arm7_processor_functions
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.long v3_tlb_fns
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.long v3_user_fns
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.long v3_cache_fns
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.size __arm710_proc_info, . - __arm710_proc_info
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