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c7a49dd42d
The SH-5 build currently fails when trying to build the i8042 code due to the missing IRQ definitions. These are provided in asm/cpu/irq.h, so just include that there to get it building again. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
57 lines
1.2 KiB
C
57 lines
1.2 KiB
C
#ifndef __ASM_SH_IRQ_H
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#define __ASM_SH_IRQ_H
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#include <asm/machvec.h>
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/*
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* A sane default based on a reasonable vector table size, platforms are
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* advised to cap this at the hard limit that they're interested in
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* through the machvec.
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*/
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#define NR_IRQS 256
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/*
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* Convert back and forth between INTEVT and IRQ values.
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*/
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#ifdef CONFIG_CPU_HAS_INTEVT
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#define evt2irq(evt) (((evt) >> 5) - 16)
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#define irq2evt(irq) (((irq) + 16) << 5)
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#else
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#define evt2irq(evt) (evt)
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#define irq2evt(irq) (irq)
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#endif
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/*
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* Simple Mask Register Support
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*/
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extern void make_maskreg_irq(unsigned int irq);
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extern unsigned short *irq_mask_register;
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/*
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* PINT IRQs
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*/
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void init_IRQ_pint(void);
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void make_imask_irq(unsigned int irq);
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static inline int generic_irq_demux(int irq)
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{
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return irq;
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}
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#define irq_canonicalize(irq) (irq)
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#define irq_demux(irq) sh_mv.mv_irq_demux(irq)
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#ifdef CONFIG_IRQSTACKS
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extern void irq_ctx_init(int cpu);
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extern void irq_ctx_exit(int cpu);
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# define __ARCH_HAS_DO_SOFTIRQ
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#else
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# define irq_ctx_init(cpu) do { } while (0)
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# define irq_ctx_exit(cpu) do { } while (0)
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#endif
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#ifdef CONFIG_CPU_SH5
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#include <asm/cpu/irq.h>
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#endif
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#endif /* __ASM_SH_IRQ_H */
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