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83 lines
3.7 KiB
Text
83 lines
3.7 KiB
Text
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Below is what the bt878 data book says about the PCI bug compatibility
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modes of the bt878 chip.
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The triton1 insmod option sets the EN_TBFX bit in the control register.
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The vsfx insmod option does the same for EN_VSFX bit. If you have
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stability problems you can try if one of these options makes your box
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work solid.
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drivers/pci/quirks.c knows about these issues, this way these bits are
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enabled automagically for known-buggy chipsets (look at the kernel
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messages, bttv tells you).
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HTH,
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Gerd
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---------------------------- cut here --------------------------
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Normal PCI Mode
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---------------
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The PCI REQ signal is the logical-or of the incoming function requests.
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The inter-nal GNT[0:1] signals are gated asynchronously with GNT and
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demultiplexed by the audio request signal. Thus the arbiter defaults to
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the video function at power-up and parks there during no requests for
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bus access. This is desirable since the video will request the bus more
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often. However, the audio will have highest bus access priority. Thus
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the audio will have first access to the bus even when issuing a request
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after the video request but before the PCI external arbiter has granted
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access to the Bt879. Neither function can preempt the other once on the
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bus. The duration to empty the entire video PCI FIFO onto the PCI bus is
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very short compared to the bus access latency the audio PCI FIFO can
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tolerate.
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430FX Compatibility Mode
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------------------------
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When using the 430FX PCI, the following rules will ensure
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compatibility:
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(1) Deassert REQ at the same time as asserting FRAME.
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(2) Do not reassert REQ to request another bus transaction until after
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finish-ing the previous transaction.
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Since the individual bus masters do not have direct control of REQ, a
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simple logical-or of video and audio requests would violate the rules.
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Thus, both the arbiter and the initiator contain 430FX compatibility
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mode logic. To enable 430FX mode, set the EN_TBFX bit as indicated in
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Device Control Register on page 104.
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When EN_TBFX is enabled, the arbiter ensures that the two compatibility
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rules are satisfied. Before GNT is asserted by the PCI arbiter, this
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internal arbiter may still logical-or the two requests. However, once
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the GNT is issued, this arbiter must lock in its decision and now route
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only the granted request to the REQ pin. The arbiter decision lock
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happens regardless of the state of FRAME because it does not know when
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FRAME will be asserted (typically - each initiator will assert FRAME on
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the cycle following GNT). When FRAME is asserted, it is the initiator s
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responsibility to remove its request at the same time. It is the
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arbiters responsibility to allow this request to flow through to REQ and
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not allow the other request to hold REQ asserted. The decision lock may
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be removed at the end of the transaction: for example, when the bus is
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idle (FRAME and IRDY). The arbiter decision may then continue
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asynchronously until GNT is again asserted.
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Interfacing with Non-PCI 2.1 Compliant Core Logic
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-------------------------------------------------
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A small percentage of core logic devices may start a bus transaction
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during the same cycle that GNT is de-asserted. This is non PCI 2.1
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compliant. To ensure compatibility when using PCs with these PCI
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controllers, the EN_VSFX bit must be enabled (refer to Device Control
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Register on page 104). When in this mode, the arbiter does not pass GNT
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to the internal functions unless REQ is asserted. This prevents a bus
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transaction from starting the same cycle as GNT is de-asserted. This
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also has the side effect of not being able to take advantage of bus
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parking, thus lowering arbitration performance. The Bt879 drivers must
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query for these non-compliant devices, and set the EN_VSFX bit only if
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required.
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