mirror of
https://github.com/adulau/aha.git
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1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
311 lines
9.1 KiB
C
311 lines
9.1 KiB
C
#ifndef __ASM_SH_IO_H
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#define __ASM_SH_IO_H
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/*
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* Convention:
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* read{b,w,l}/write{b,w,l} are for PCI,
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* while in{b,w,l}/out{b,w,l} are for ISA
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* These may (will) be platform specific function.
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* In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p
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* and 'string' versions: ins{b,w,l}/outs{b,w,l}
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* For read{b,w,l} and write{b,w,l} there are also __raw versions, which
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* do not have a memory barrier after them.
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*
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* In addition, we have
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* ctrl_in{b,w,l}/ctrl_out{b,w,l} for SuperH specific I/O.
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* which are processor specific.
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*/
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/*
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* We follow the Alpha convention here:
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* __inb expands to an inline function call (which calls via the mv)
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* _inb is a real function call (note ___raw fns are _ version of __raw)
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* inb by default expands to _inb, but the machine specific code may
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* define it to __inb if it chooses.
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*/
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#include <asm/cache.h>
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#include <asm/system.h>
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#include <asm/addrspace.h>
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#include <asm/machvec.h>
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#include <linux/config.h>
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/*
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* Depending on which platform we are running on, we need different
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* I/O functions.
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*/
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#ifdef __KERNEL__
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/*
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* Since boards are able to define their own set of I/O routines through
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* their respective machine vector, we always wrap through the mv.
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*
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* Also, in the event that a board hasn't provided its own definition for
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* a given routine, it will be wrapped to generic code at run-time.
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*/
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# define __inb(p) sh_mv.mv_inb((p))
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# define __inw(p) sh_mv.mv_inw((p))
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# define __inl(p) sh_mv.mv_inl((p))
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# define __outb(x,p) sh_mv.mv_outb((x),(p))
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# define __outw(x,p) sh_mv.mv_outw((x),(p))
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# define __outl(x,p) sh_mv.mv_outl((x),(p))
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# define __inb_p(p) sh_mv.mv_inb_p((p))
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# define __inw_p(p) sh_mv.mv_inw_p((p))
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# define __inl_p(p) sh_mv.mv_inl_p((p))
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# define __outb_p(x,p) sh_mv.mv_outb_p((x),(p))
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# define __outw_p(x,p) sh_mv.mv_outw_p((x),(p))
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# define __outl_p(x,p) sh_mv.mv_outl_p((x),(p))
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# define __insb(p,b,c) sh_mv.mv_insb((p), (b), (c))
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# define __insw(p,b,c) sh_mv.mv_insw((p), (b), (c))
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# define __insl(p,b,c) sh_mv.mv_insl((p), (b), (c))
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# define __outsb(p,b,c) sh_mv.mv_outsb((p), (b), (c))
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# define __outsw(p,b,c) sh_mv.mv_outsw((p), (b), (c))
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# define __outsl(p,b,c) sh_mv.mv_outsl((p), (b), (c))
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# define __readb(a) sh_mv.mv_readb((a))
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# define __readw(a) sh_mv.mv_readw((a))
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# define __readl(a) sh_mv.mv_readl((a))
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# define __writeb(v,a) sh_mv.mv_writeb((v),(a))
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# define __writew(v,a) sh_mv.mv_writew((v),(a))
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# define __writel(v,a) sh_mv.mv_writel((v),(a))
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# define __ioremap(a,s) sh_mv.mv_ioremap((a), (s))
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# define __iounmap(a) sh_mv.mv_iounmap((a))
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# define __isa_port2addr(a) sh_mv.mv_isa_port2addr(a)
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# define inb __inb
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# define inw __inw
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# define inl __inl
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# define outb __outb
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# define outw __outw
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# define outl __outl
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# define inb_p __inb_p
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# define inw_p __inw_p
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# define inl_p __inl_p
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# define outb_p __outb_p
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# define outw_p __outw_p
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# define outl_p __outl_p
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# define insb __insb
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# define insw __insw
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# define insl __insl
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# define outsb __outsb
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# define outsw __outsw
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# define outsl __outsl
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# define __raw_readb __readb
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# define __raw_readw __readw
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# define __raw_readl __readl
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# define __raw_writeb __writeb
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# define __raw_writew __writew
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# define __raw_writel __writel
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/*
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* The platform header files may define some of these macros to use
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* the inlined versions where appropriate. These macros may also be
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* redefined by userlevel programs.
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*/
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#ifdef __raw_readb
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# define readb(a) ({ unsigned long r_ = __raw_readb((unsigned long)a); mb(); r_; })
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#endif
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#ifdef __raw_readw
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# define readw(a) ({ unsigned long r_ = __raw_readw((unsigned long)a); mb(); r_; })
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#endif
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#ifdef __raw_readl
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# define readl(a) ({ unsigned long r_ = __raw_readl((unsigned long)a); mb(); r_; })
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#endif
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#ifdef __raw_writeb
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# define writeb(v,a) ({ __raw_writeb((v),(unsigned long)(a)); mb(); })
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#endif
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#ifdef __raw_writew
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# define writew(v,a) ({ __raw_writew((v),(unsigned long)(a)); mb(); })
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#endif
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#ifdef __raw_writel
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# define writel(v,a) ({ __raw_writel((v),(unsigned long)(a)); mb(); })
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#endif
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#define readb_relaxed(a) readb(a)
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#define readw_relaxed(a) readw(a)
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#define readl_relaxed(a) readl(a)
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#define mmiowb()
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/*
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* If the platform has PC-like I/O, this function converts the offset into
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* an address.
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*/
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static __inline__ unsigned long isa_port2addr(unsigned long offset)
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{
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return __isa_port2addr(offset);
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}
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/*
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* This function provides a method for the generic case where a board-specific
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* isa_port2addr simply needs to return the port + some arbitrary port base.
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*
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* We use this at board setup time to implicitly set the port base, and
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* as a result, we can use the generic isa_port2addr.
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*/
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static inline void __set_io_port_base(unsigned long pbase)
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{
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extern unsigned long generic_io_base;
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generic_io_base = pbase;
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}
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#define isa_readb(a) readb(isa_port2addr(a))
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#define isa_readw(a) readw(isa_port2addr(a))
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#define isa_readl(a) readl(isa_port2addr(a))
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#define isa_writeb(b,a) writeb(b,isa_port2addr(a))
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#define isa_writew(w,a) writew(w,isa_port2addr(a))
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#define isa_writel(l,a) writel(l,isa_port2addr(a))
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#define isa_memset_io(a,b,c) \
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memset((void *)(isa_port2addr((unsigned long)a)),(b),(c))
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#define isa_memcpy_fromio(a,b,c) \
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memcpy((a),(void *)(isa_port2addr((unsigned long)(b))),(c))
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#define isa_memcpy_toio(a,b,c) \
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memcpy((void *)(isa_port2addr((unsigned long)(a))),(b),(c))
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/* We really want to try and get these to memcpy etc */
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extern void memcpy_fromio(void *, unsigned long, unsigned long);
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extern void memcpy_toio(unsigned long, const void *, unsigned long);
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extern void memset_io(unsigned long, int, unsigned long);
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/* SuperH on-chip I/O functions */
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static __inline__ unsigned char ctrl_inb(unsigned long addr)
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{
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return *(volatile unsigned char*)addr;
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}
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static __inline__ unsigned short ctrl_inw(unsigned long addr)
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{
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return *(volatile unsigned short*)addr;
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}
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static __inline__ unsigned int ctrl_inl(unsigned long addr)
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{
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return *(volatile unsigned long*)addr;
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}
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static __inline__ void ctrl_outb(unsigned char b, unsigned long addr)
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{
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*(volatile unsigned char*)addr = b;
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}
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static __inline__ void ctrl_outw(unsigned short b, unsigned long addr)
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{
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*(volatile unsigned short*)addr = b;
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}
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static __inline__ void ctrl_outl(unsigned int b, unsigned long addr)
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{
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*(volatile unsigned long*)addr = b;
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}
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#define IO_SPACE_LIMIT 0xffffffff
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/*
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* Change virtual addresses to physical addresses and vv.
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* These are trivial on the 1:1 Linux/SuperH mapping
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*/
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static __inline__ unsigned long virt_to_phys(volatile void * address)
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{
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return PHYSADDR(address);
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}
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static __inline__ void * phys_to_virt(unsigned long address)
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{
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return (void *)P1SEGADDR(address);
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}
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#define virt_to_bus virt_to_phys
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#define bus_to_virt phys_to_virt
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#define page_to_bus page_to_phys
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/*
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* readX/writeX() are used to access memory mapped devices. On some
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* architectures the memory mapped IO stuff needs to be accessed
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* differently. On the x86 architecture, we just read/write the
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* memory location directly.
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*
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* On SH, we have the whole physical address space mapped at all times
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* (as MIPS does), so "ioremap()" and "iounmap()" do not need to do
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* anything. (This isn't true for all machines but we still handle
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* these cases with wired TLB entries anyway ...)
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*
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* We cheat a bit and always return uncachable areas until we've fixed
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* the drivers to handle caching properly.
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*/
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static __inline__ void * ioremap(unsigned long offset, unsigned long size)
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{
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return __ioremap(offset, size);
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}
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static __inline__ void iounmap(void *addr)
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{
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return __iounmap(addr);
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}
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#define ioremap_nocache(off,size) ioremap(off,size)
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static __inline__ int check_signature(unsigned long io_addr,
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const unsigned char *signature, int length)
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{
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int retval = 0;
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do {
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if (readb(io_addr) != *signature)
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goto out;
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io_addr++;
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signature++;
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length--;
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} while (length);
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retval = 1;
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out:
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return retval;
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}
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/*
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* The caches on some architectures aren't dma-coherent and have need to
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* handle this in software. There are three types of operations that
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* can be applied to dma buffers.
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*
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* - dma_cache_wback_inv(start, size) makes caches and RAM coherent by
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* writing the content of the caches back to memory, if necessary.
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* The function also invalidates the affected part of the caches as
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* necessary before DMA transfers from outside to memory.
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* - dma_cache_inv(start, size) invalidates the affected parts of the
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* caches. Dirty lines of the caches may be written back or simply
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* be discarded. This operation is necessary before dma operations
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* to the memory.
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* - dma_cache_wback(start, size) writes back any dirty lines but does
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* not invalidate the cache. This can be used before DMA reads from
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* memory,
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*/
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#define dma_cache_wback_inv(_start,_size) \
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__flush_purge_region(_start,_size)
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#define dma_cache_inv(_start,_size) \
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__flush_invalidate_region(_start,_size)
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#define dma_cache_wback(_start,_size) \
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__flush_wback_region(_start,_size)
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/*
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* Convert a physical pointer to a virtual kernel pointer for /dev/mem
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* access
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*/
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#define xlate_dev_mem_ptr(p) __va(p)
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/*
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* Convert a virtual cached pointer to an uncached pointer
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*/
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#define xlate_dev_kmem_ptr(p) p
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#endif /* __KERNEL__ */
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#endif /* __ASM_SH_IO_H */
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