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1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
206 lines
7.4 KiB
C
206 lines
7.4 KiB
C
#ifndef __SOUND_AD1848_H
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#define __SOUND_AD1848_H
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/*
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* Copyright (c) by Jaroslav Kysela <perex@suse.cz>
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* Definitions for AD1847/AD1848/CS4248 chips
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include "pcm.h"
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#include <linux/interrupt.h>
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/* IO ports */
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#define AD1848P( codec, x ) ( (chip) -> port + c_d_c_AD1848##x )
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#define c_d_c_AD1848REGSEL 0
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#define c_d_c_AD1848REG 1
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#define c_d_c_AD1848STATUS 2
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#define c_d_c_AD1848PIO 3
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/* codec registers */
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#define AD1848_LEFT_INPUT 0x00 /* left input control */
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#define AD1848_RIGHT_INPUT 0x01 /* right input control */
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#define AD1848_AUX1_LEFT_INPUT 0x02 /* left AUX1 input control */
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#define AD1848_AUX1_RIGHT_INPUT 0x03 /* right AUX1 input control */
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#define AD1848_AUX2_LEFT_INPUT 0x04 /* left AUX2 input control */
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#define AD1848_AUX2_RIGHT_INPUT 0x05 /* right AUX2 input control */
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#define AD1848_LEFT_OUTPUT 0x06 /* left output control register */
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#define AD1848_RIGHT_OUTPUT 0x07 /* right output control register */
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#define AD1848_DATA_FORMAT 0x08 /* clock and data format - playback/capture - bits 7-0 MCE */
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#define AD1848_IFACE_CTRL 0x09 /* interface control - bits 7-2 MCE */
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#define AD1848_PIN_CTRL 0x0a /* pin control */
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#define AD1848_TEST_INIT 0x0b /* test and initialization */
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#define AD1848_MISC_INFO 0x0c /* miscellaneaous information */
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#define AD1848_LOOPBACK 0x0d /* loopback control */
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#define AD1848_DATA_UPR_CNT 0x0e /* playback/capture upper base count */
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#define AD1848_DATA_LWR_CNT 0x0f /* playback/capture lower base count */
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/* definitions for codec register select port - CODECP( REGSEL ) */
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#define AD1848_INIT 0x80 /* CODEC is initializing */
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#define AD1848_MCE 0x40 /* mode change enable */
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#define AD1848_TRD 0x20 /* transfer request disable */
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/* definitions for codec status register - CODECP( STATUS ) */
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#define AD1848_GLOBALIRQ 0x01 /* IRQ is active */
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/* definitions for AD1848_LEFT_INPUT and AD1848_RIGHT_INPUT registers */
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#define AD1848_ENABLE_MIC_GAIN 0x20
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#define AD1848_MIXS_LINE1 0x00
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#define AD1848_MIXS_AUX1 0x40
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#define AD1848_MIXS_LINE2 0x80
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#define AD1848_MIXS_ALL 0xc0
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/* definitions for clock and data format register - AD1848_PLAYBK_FORMAT */
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#define AD1848_LINEAR_8 0x00 /* 8-bit unsigned data */
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#define AD1848_ALAW_8 0x60 /* 8-bit A-law companded */
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#define AD1848_ULAW_8 0x20 /* 8-bit U-law companded */
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#define AD1848_LINEAR_16 0x40 /* 16-bit twos complement data - little endian */
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#define AD1848_STEREO 0x10 /* stereo mode */
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/* bits 3-1 define frequency divisor */
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#define AD1848_XTAL1 0x00 /* 24.576 crystal */
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#define AD1848_XTAL2 0x01 /* 16.9344 crystal */
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/* definitions for interface control register - AD1848_IFACE_CTRL */
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#define AD1848_CAPTURE_PIO 0x80 /* capture PIO enable */
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#define AD1848_PLAYBACK_PIO 0x40 /* playback PIO enable */
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#define AD1848_CALIB_MODE 0x18 /* calibration mode bits */
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#define AD1848_AUTOCALIB 0x08 /* auto calibrate */
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#define AD1848_SINGLE_DMA 0x04 /* use single DMA channel */
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#define AD1848_CAPTURE_ENABLE 0x02 /* capture enable */
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#define AD1848_PLAYBACK_ENABLE 0x01 /* playback enable */
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/* definitions for pin control register - AD1848_PIN_CTRL */
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#define AD1848_IRQ_ENABLE 0x02 /* enable IRQ */
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#define AD1848_XCTL1 0x40 /* external control #1 */
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#define AD1848_XCTL0 0x80 /* external control #0 */
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/* definitions for test and init register - AD1848_TEST_INIT */
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#define AD1848_CALIB_IN_PROGRESS 0x20 /* auto calibrate in progress */
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#define AD1848_DMA_REQUEST 0x10 /* DMA request in progress */
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/* defines for codec.mode */
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#define AD1848_MODE_NONE 0x0000
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#define AD1848_MODE_PLAY 0x0001
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#define AD1848_MODE_CAPTURE 0x0002
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#define AD1848_MODE_TIMER 0x0004
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#define AD1848_MODE_OPEN (AD1848_MODE_PLAY|AD1848_MODE_CAPTURE|AD1848_MODE_TIMER)
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#define AD1848_MODE_RUNNING 0x0010
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/* defines for codec.hardware */
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#define AD1848_HW_DETECT 0x0000 /* let AD1848 driver detect chip */
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#define AD1848_HW_AD1847 0x0001 /* AD1847 chip */
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#define AD1848_HW_AD1848 0x0002 /* AD1848 chip */
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#define AD1848_HW_CS4248 0x0003 /* CS4248 chip */
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#define AD1848_HW_CMI8330 0x0004 /* CMI8330 chip */
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#define AD1848_HW_THINKPAD 0x0005 /* Thinkpad 360/750/755 */
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/* IBM Thinkpad specific stuff */
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#define AD1848_THINKPAD_CTL_PORT1 0x15e8
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#define AD1848_THINKPAD_CTL_PORT2 0x15e9
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#define AD1848_THINKPAD_CS4248_ENABLE_BIT 0x02
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struct _snd_ad1848 {
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unsigned long port; /* i/o port */
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struct resource *res_port;
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int irq; /* IRQ line */
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int dma; /* data DMA */
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unsigned short version; /* version of CODEC chip */
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unsigned short mode; /* see to AD1848_MODE_XXXX */
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unsigned short hardware; /* see to AD1848_HW_XXXX */
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unsigned short single_dma:1; /* forced single DMA mode (GUS 16-bit daughter board) or dma1 == dma2 */
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snd_pcm_t *pcm;
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snd_pcm_substream_t *playback_substream;
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snd_pcm_substream_t *capture_substream;
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snd_card_t *card;
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unsigned char image[32]; /* SGalaxy needs an access to extended registers */
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int mce_bit;
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int calibrate_mute;
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int dma_size;
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int thinkpad_flag; /* Thinkpad CS4248 needs some extra help */
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spinlock_t reg_lock;
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struct semaphore open_mutex;
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};
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typedef struct _snd_ad1848 ad1848_t;
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/* exported functions */
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void snd_ad1848_out(ad1848_t *chip, unsigned char reg, unsigned char value);
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int snd_ad1848_create(snd_card_t * card,
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unsigned long port,
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int irq, int dma,
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unsigned short hardware,
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ad1848_t ** chip);
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int snd_ad1848_pcm(ad1848_t * chip, int device, snd_pcm_t **rpcm);
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const snd_pcm_ops_t *snd_ad1848_get_pcm_ops(int direction);
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int snd_ad1848_mixer(ad1848_t * chip);
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/* exported mixer stuffs */
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enum { AD1848_MIX_SINGLE, AD1848_MIX_DOUBLE, AD1848_MIX_CAPTURE };
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#define AD1848_MIXVAL_SINGLE(reg, shift, mask, invert) \
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((reg) | ((shift) << 8) | ((mask) << 16) | ((invert) << 24))
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#define AD1848_MIXVAL_DOUBLE(left_reg, right_reg, shift_left, shift_right, mask, invert) \
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((left_reg) | ((right_reg) << 8) | ((shift_left) << 16) | ((shift_right) << 19) | ((mask) << 24) | ((invert) << 22))
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int snd_ad1848_add_ctl(ad1848_t *chip, const char *name, int index, int type, unsigned long value);
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/* for ease of use */
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struct ad1848_mix_elem {
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const char *name;
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int index;
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int type;
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unsigned long private_value;
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};
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#define AD1848_SINGLE(xname, xindex, reg, shift, mask, invert) \
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{ .name = xname, \
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.index = xindex, \
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.type = AD1848_MIX_SINGLE, \
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.private_value = AD1848_MIXVAL_SINGLE(reg, shift, mask, invert) }
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#define AD1848_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \
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{ .name = xname, \
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.index = xindex, \
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.type = AD1848_MIX_DOUBLE, \
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.private_value = AD1848_MIXVAL_DOUBLE(left_reg, right_reg, shift_left, shift_right, mask, invert) }
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static inline int snd_ad1848_add_ctl_elem(ad1848_t *chip, const struct ad1848_mix_elem *c)
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{
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return snd_ad1848_add_ctl(chip, c->name, c->index, c->type, c->private_value);
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}
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#endif /* __SOUND_AD1848_H */
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