mirror of
https://github.com/adulau/aha.git
synced 2024-12-30 20:56:23 +00:00
861fe90656
Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
57 lines
1.6 KiB
C
57 lines
1.6 KiB
C
/* $Id: iommu.h,v 1.10 2001/03/08 09:55:56 davem Exp $
|
|
* iommu.h: Definitions for the sun5 IOMMU.
|
|
*
|
|
* Copyright (C) 1996, 1999 David S. Miller (davem@caip.rutgers.edu)
|
|
*/
|
|
#ifndef _SPARC64_IOMMU_H
|
|
#define _SPARC64_IOMMU_H
|
|
|
|
/* The format of an iopte in the page tables. */
|
|
#define IOPTE_VALID 0x8000000000000000UL
|
|
#define IOPTE_64K 0x2000000000000000UL
|
|
#define IOPTE_STBUF 0x1000000000000000UL
|
|
#define IOPTE_INTRA 0x0800000000000000UL
|
|
#define IOPTE_CONTEXT 0x07ff800000000000UL
|
|
#define IOPTE_PAGE 0x00007fffffffe000UL
|
|
#define IOPTE_CACHE 0x0000000000000010UL
|
|
#define IOPTE_WRITE 0x0000000000000002UL
|
|
|
|
#define IOMMU_NUM_CTXS 4096
|
|
|
|
struct iommu_arena {
|
|
unsigned long *map;
|
|
unsigned int hint;
|
|
unsigned int limit;
|
|
};
|
|
|
|
struct iommu {
|
|
spinlock_t lock;
|
|
struct iommu_arena arena;
|
|
iopte_t *page_table;
|
|
u32 page_table_map_base;
|
|
unsigned long iommu_control;
|
|
unsigned long iommu_tsbbase;
|
|
unsigned long iommu_flush;
|
|
unsigned long iommu_flushinv;
|
|
unsigned long iommu_ctxflush;
|
|
unsigned long write_complete_reg;
|
|
unsigned long dummy_page;
|
|
unsigned long dummy_page_pa;
|
|
unsigned long ctx_lowest_free;
|
|
DECLARE_BITMAP(ctx_bitmap, IOMMU_NUM_CTXS);
|
|
u32 dma_addr_mask;
|
|
};
|
|
|
|
struct strbuf {
|
|
int strbuf_enabled;
|
|
unsigned long strbuf_control;
|
|
unsigned long strbuf_pflush;
|
|
unsigned long strbuf_fsync;
|
|
unsigned long strbuf_ctxflush;
|
|
unsigned long strbuf_ctxmatch_base;
|
|
unsigned long strbuf_flushflag_pa;
|
|
volatile unsigned long *strbuf_flushflag;
|
|
volatile unsigned long __flushflag_buf[(64+(64-1)) / sizeof(long)];
|
|
};
|
|
|
|
#endif /* !(_SPARC_IOMMU_H) */
|