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20b0166988
This patch adds support and enables state C4(MPU RET + CORE RET) and MPU OFF states (C3 and C5.) Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
259 lines
7.9 KiB
C
259 lines
7.9 KiB
C
/*
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* linux/arch/arm/mach-omap2/cpuidle34xx.c
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*
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* OMAP3 CPU IDLE Routines
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*
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* Copyright (C) 2008 Texas Instruments, Inc.
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* Rajendra Nayak <rnayak@ti.com>
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*
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* Copyright (C) 2007 Texas Instruments, Inc.
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* Karthik Dasu <karthik-dp@ti.com>
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*
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* Copyright (C) 2006 Nokia Corporation
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* Tony Lindgren <tony@atomide.com>
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*
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* Copyright (C) 2005 Texas Instruments, Inc.
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* Based on pm.c for omap2
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/cpuidle.h>
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#include <plat/prcm.h>
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#include <plat/powerdomain.h>
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#include <plat/irqs.h>
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#include <plat/control.h>
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#ifdef CONFIG_CPU_IDLE
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#define OMAP3_MAX_STATES 7
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#define OMAP3_STATE_C1 1 /* C1 - MPU WFI + Core active */
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#define OMAP3_STATE_C2 2 /* C2 - MPU CSWR + Core active */
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#define OMAP3_STATE_C3 3 /* C3 - MPU OFF + Core active */
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#define OMAP3_STATE_C4 4 /* C4 - MPU RET + Core RET */
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#define OMAP3_STATE_C5 5 /* C5 - MPU OFF + Core RET */
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#define OMAP3_STATE_C6 6 /* C6 - MPU OFF + Core OFF */
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struct omap3_processor_cx {
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u8 valid;
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u8 type;
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u32 sleep_latency;
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u32 wakeup_latency;
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u32 mpu_state;
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u32 core_state;
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u32 threshold;
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u32 flags;
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};
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struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];
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struct omap3_processor_cx current_cx_state;
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struct powerdomain *mpu_pd, *core_pd;
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static int omap3_idle_bm_check(void)
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{
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if (!omap3_can_sleep())
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return 1;
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return 0;
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}
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/**
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* omap3_enter_idle - Programs OMAP3 to enter the specified state
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* @dev: cpuidle device
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* @state: The target state to be programmed
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*
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* Called from the CPUidle framework to program the device to the
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* specified target state selected by the governor.
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*/
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static int omap3_enter_idle(struct cpuidle_device *dev,
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struct cpuidle_state *state)
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{
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struct omap3_processor_cx *cx = cpuidle_get_statedata(state);
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struct timespec ts_preidle, ts_postidle, ts_idle;
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current_cx_state = *cx;
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/* Used to keep track of the total time in idle */
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getnstimeofday(&ts_preidle);
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local_irq_disable();
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local_fiq_disable();
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set_pwrdm_state(mpu_pd, cx->mpu_state);
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set_pwrdm_state(core_pd, cx->core_state);
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if (omap_irq_pending())
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goto return_sleep_time;
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/* Execute ARM wfi */
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omap_sram_idle();
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return_sleep_time:
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getnstimeofday(&ts_postidle);
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ts_idle = timespec_sub(ts_postidle, ts_preidle);
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local_irq_enable();
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local_fiq_enable();
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return (u32)timespec_to_ns(&ts_idle)/1000;
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}
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/**
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* omap3_enter_idle_bm - Checks for any bus activity
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* @dev: cpuidle device
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* @state: The target state to be programmed
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*
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* Used for C states with CPUIDLE_FLAG_CHECK_BM flag set. This
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* function checks for any pending activity and then programs the
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* device to the specified or a safer state.
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*/
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static int omap3_enter_idle_bm(struct cpuidle_device *dev,
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struct cpuidle_state *state)
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{
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if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) {
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if (dev->safe_state)
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return dev->safe_state->enter(dev, dev->safe_state);
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}
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return omap3_enter_idle(dev, state);
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}
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DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
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/* omap3_init_power_states - Initialises the OMAP3 specific C states.
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*
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* Below is the desciption of each C state.
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* C1 . MPU WFI + Core active
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* C2 . MPU CSWR + Core active
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* C3 . MPU OFF + Core active
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* C4 . MPU CSWR + Core CSWR
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* C5 . MPU OFF + Core CSWR
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* C6 . MPU OFF + Core OFF
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*/
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void omap_init_power_states(void)
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{
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/* C1 . MPU WFI + Core active */
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omap3_power_states[OMAP3_STATE_C1].valid = 1;
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omap3_power_states[OMAP3_STATE_C1].type = OMAP3_STATE_C1;
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omap3_power_states[OMAP3_STATE_C1].sleep_latency = 10;
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omap3_power_states[OMAP3_STATE_C1].wakeup_latency = 10;
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omap3_power_states[OMAP3_STATE_C1].threshold = 30;
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omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON;
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omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON;
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omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID;
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/* C2 . MPU CSWR + Core active */
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omap3_power_states[OMAP3_STATE_C2].valid = 1;
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omap3_power_states[OMAP3_STATE_C2].type = OMAP3_STATE_C2;
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omap3_power_states[OMAP3_STATE_C2].sleep_latency = 50;
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omap3_power_states[OMAP3_STATE_C2].wakeup_latency = 50;
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omap3_power_states[OMAP3_STATE_C2].threshold = 300;
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omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_RET;
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omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON;
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omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID;
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/* C3 . MPU OFF + Core active */
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omap3_power_states[OMAP3_STATE_C3].valid = 1;
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omap3_power_states[OMAP3_STATE_C3].type = OMAP3_STATE_C3;
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omap3_power_states[OMAP3_STATE_C3].sleep_latency = 1500;
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omap3_power_states[OMAP3_STATE_C3].wakeup_latency = 1800;
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omap3_power_states[OMAP3_STATE_C3].threshold = 4000;
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omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_OFF;
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omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON;
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omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID;
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/* C4 . MPU CSWR + Core CSWR*/
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omap3_power_states[OMAP3_STATE_C4].valid = 1;
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omap3_power_states[OMAP3_STATE_C4].type = OMAP3_STATE_C4;
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omap3_power_states[OMAP3_STATE_C4].sleep_latency = 2500;
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omap3_power_states[OMAP3_STATE_C4].wakeup_latency = 7500;
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omap3_power_states[OMAP3_STATE_C4].threshold = 12000;
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omap3_power_states[OMAP3_STATE_C4].mpu_state = PWRDM_POWER_RET;
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omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_RET;
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omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID |
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CPUIDLE_FLAG_CHECK_BM;
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/* C5 . MPU OFF + Core CSWR */
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omap3_power_states[OMAP3_STATE_C5].valid = 1;
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omap3_power_states[OMAP3_STATE_C5].type = OMAP3_STATE_C5;
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omap3_power_states[OMAP3_STATE_C5].sleep_latency = 3000;
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omap3_power_states[OMAP3_STATE_C5].wakeup_latency = 8500;
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omap3_power_states[OMAP3_STATE_C5].threshold = 15000;
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omap3_power_states[OMAP3_STATE_C5].mpu_state = PWRDM_POWER_OFF;
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omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET;
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omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID |
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CPUIDLE_FLAG_CHECK_BM;
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/* C6 . MPU OFF + Core OFF */
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omap3_power_states[OMAP3_STATE_C6].valid = 0;
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omap3_power_states[OMAP3_STATE_C6].type = OMAP3_STATE_C6;
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omap3_power_states[OMAP3_STATE_C6].sleep_latency = 10000;
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omap3_power_states[OMAP3_STATE_C6].wakeup_latency = 30000;
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omap3_power_states[OMAP3_STATE_C6].threshold = 300000;
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omap3_power_states[OMAP3_STATE_C6].mpu_state = PWRDM_POWER_OFF;
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omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_OFF;
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omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID |
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CPUIDLE_FLAG_CHECK_BM;
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}
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struct cpuidle_driver omap3_idle_driver = {
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.name = "omap3_idle",
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.owner = THIS_MODULE,
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};
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/**
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* omap3_idle_init - Init routine for OMAP3 idle
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*
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* Registers the OMAP3 specific cpuidle driver with the cpuidle
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* framework with the valid set of states.
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*/
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int omap3_idle_init(void)
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{
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int i, count = 0;
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struct omap3_processor_cx *cx;
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struct cpuidle_state *state;
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struct cpuidle_device *dev;
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mpu_pd = pwrdm_lookup("mpu_pwrdm");
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core_pd = pwrdm_lookup("core_pwrdm");
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omap_init_power_states();
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cpuidle_register_driver(&omap3_idle_driver);
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dev = &per_cpu(omap3_idle_dev, smp_processor_id());
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for (i = 1; i < OMAP3_MAX_STATES; i++) {
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cx = &omap3_power_states[i];
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state = &dev->states[count];
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if (!cx->valid)
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continue;
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cpuidle_set_statedata(state, cx);
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state->exit_latency = cx->sleep_latency + cx->wakeup_latency;
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state->target_residency = cx->threshold;
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state->flags = cx->flags;
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state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ?
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omap3_enter_idle_bm : omap3_enter_idle;
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if (cx->type == OMAP3_STATE_C1)
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dev->safe_state = state;
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sprintf(state->name, "C%d", count+1);
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count++;
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}
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if (!count)
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return -EINVAL;
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dev->state_count = count;
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if (cpuidle_register_device(dev)) {
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printk(KERN_ERR "%s: CPUidle register device failed\n",
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__func__);
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return -EIO;
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}
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return 0;
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}
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device_initcall(omap3_idle_init);
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#endif /* CONFIG_CPU_IDLE */
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