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https://github.com/adulau/aha.git
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c07f87f22e
Add power management support to the VIC by registering each VIC as a system device to get suspend/resume events going. Since the VIC registeration is done early, we need to record the VICs in a static array which is used to add the system devices later once the initcalls are run. This means there is now a configuration value for the number of VICs in the system. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
256 lines
6.1 KiB
C
256 lines
6.1 KiB
C
/* arch/arm/plat-s3c64xx/irq.c
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C64XX - Interrupt handling
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/serial_core.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/hardware/vic.h>
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#include <mach/map.h>
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#include <plat/regs-serial.h>
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#include <plat/regs-timer.h>
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#include <plat/cpu.h>
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/* Timer interrupt handling */
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static void s3c_irq_demux_timer(unsigned int base_irq, unsigned int sub_irq)
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{
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generic_handle_irq(sub_irq);
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}
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static void s3c_irq_demux_timer0(unsigned int irq, struct irq_desc *desc)
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{
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s3c_irq_demux_timer(irq, IRQ_TIMER0);
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}
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static void s3c_irq_demux_timer1(unsigned int irq, struct irq_desc *desc)
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{
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s3c_irq_demux_timer(irq, IRQ_TIMER1);
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}
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static void s3c_irq_demux_timer2(unsigned int irq, struct irq_desc *desc)
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{
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s3c_irq_demux_timer(irq, IRQ_TIMER2);
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}
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static void s3c_irq_demux_timer3(unsigned int irq, struct irq_desc *desc)
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{
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s3c_irq_demux_timer(irq, IRQ_TIMER3);
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}
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static void s3c_irq_demux_timer4(unsigned int irq, struct irq_desc *desc)
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{
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s3c_irq_demux_timer(irq, IRQ_TIMER4);
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}
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/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
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static void s3c_irq_timer_mask(unsigned int irq)
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{
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u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
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reg &= 0x1f; /* mask out pending interrupts */
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reg &= ~(1 << (irq - IRQ_TIMER0));
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__raw_writel(reg, S3C64XX_TINT_CSTAT);
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}
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static void s3c_irq_timer_unmask(unsigned int irq)
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{
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u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
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reg &= 0x1f; /* mask out pending interrupts */
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reg |= 1 << (irq - IRQ_TIMER0);
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__raw_writel(reg, S3C64XX_TINT_CSTAT);
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}
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static void s3c_irq_timer_ack(unsigned int irq)
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{
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u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
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reg &= 0x1f;
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reg |= (1 << 5) << (irq - IRQ_TIMER0);
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__raw_writel(reg, S3C64XX_TINT_CSTAT);
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}
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static struct irq_chip s3c_irq_timer = {
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.name = "s3c-timer",
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.mask = s3c_irq_timer_mask,
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.unmask = s3c_irq_timer_unmask,
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.ack = s3c_irq_timer_ack,
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};
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struct uart_irq {
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void __iomem *regs;
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unsigned int base_irq;
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unsigned int parent_irq;
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};
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/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
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* are consecutive when looking up the interrupt in the demux routines.
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*/
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static struct uart_irq uart_irqs[] = {
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[0] = {
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.regs = S3C_VA_UART0,
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.base_irq = IRQ_S3CUART_BASE0,
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.parent_irq = IRQ_UART0,
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},
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[1] = {
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.regs = S3C_VA_UART1,
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.base_irq = IRQ_S3CUART_BASE1,
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.parent_irq = IRQ_UART1,
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},
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[2] = {
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.regs = S3C_VA_UART2,
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.base_irq = IRQ_S3CUART_BASE2,
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.parent_irq = IRQ_UART2,
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},
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[3] = {
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.regs = S3C_VA_UART3,
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.base_irq = IRQ_S3CUART_BASE3,
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.parent_irq = IRQ_UART3,
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},
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};
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static inline void __iomem *s3c_irq_uart_base(unsigned int irq)
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{
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struct uart_irq *uirq = get_irq_chip_data(irq);
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return uirq->regs;
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}
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static inline unsigned int s3c_irq_uart_bit(unsigned int irq)
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{
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return irq & 3;
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}
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/* UART interrupt registers, not worth adding to seperate include header */
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static void s3c_irq_uart_mask(unsigned int irq)
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{
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void __iomem *regs = s3c_irq_uart_base(irq);
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unsigned int bit = s3c_irq_uart_bit(irq);
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u32 reg;
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reg = __raw_readl(regs + S3C64XX_UINTM);
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reg |= (1 << bit);
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__raw_writel(reg, regs + S3C64XX_UINTM);
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}
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static void s3c_irq_uart_maskack(unsigned int irq)
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{
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void __iomem *regs = s3c_irq_uart_base(irq);
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unsigned int bit = s3c_irq_uart_bit(irq);
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u32 reg;
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reg = __raw_readl(regs + S3C64XX_UINTM);
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reg |= (1 << bit);
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__raw_writel(reg, regs + S3C64XX_UINTM);
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__raw_writel(1 << bit, regs + S3C64XX_UINTP);
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}
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static void s3c_irq_uart_unmask(unsigned int irq)
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{
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void __iomem *regs = s3c_irq_uart_base(irq);
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unsigned int bit = s3c_irq_uart_bit(irq);
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u32 reg;
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reg = __raw_readl(regs + S3C64XX_UINTM);
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reg &= ~(1 << bit);
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__raw_writel(reg, regs + S3C64XX_UINTM);
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}
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static void s3c_irq_uart_ack(unsigned int irq)
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{
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void __iomem *regs = s3c_irq_uart_base(irq);
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unsigned int bit = s3c_irq_uart_bit(irq);
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__raw_writel(1 << bit, regs + S3C64XX_UINTP);
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}
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static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
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{
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struct uart_irq *uirq = &uart_irqs[irq - IRQ_UART0];
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u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP);
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int base = uirq->base_irq;
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if (pend & (1 << 0))
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generic_handle_irq(base);
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if (pend & (1 << 1))
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generic_handle_irq(base + 1);
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if (pend & (1 << 2))
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generic_handle_irq(base + 2);
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if (pend & (1 << 3))
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generic_handle_irq(base + 3);
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}
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static struct irq_chip s3c_irq_uart = {
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.name = "s3c-uart",
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.mask = s3c_irq_uart_mask,
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.unmask = s3c_irq_uart_unmask,
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.mask_ack = s3c_irq_uart_maskack,
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.ack = s3c_irq_uart_ack,
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};
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static void __init s3c64xx_uart_irq(struct uart_irq *uirq)
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{
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void __iomem *reg_base = uirq->regs;
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unsigned int irq;
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int offs;
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/* mask all interrupts at the start. */
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__raw_writel(0xf, reg_base + S3C64XX_UINTM);
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for (offs = 0; offs < 3; offs++) {
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irq = uirq->base_irq + offs;
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set_irq_chip(irq, &s3c_irq_uart);
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set_irq_chip_data(irq, uirq);
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set_irq_handler(irq, handle_level_irq);
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set_irq_flags(irq, IRQF_VALID);
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}
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set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart);
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}
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void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
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{
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int uart, irq;
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printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
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/* initialise the pair of VICs */
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vic_init(S3C_VA_VIC0, S3C_VIC0_BASE, vic0_valid, 0);
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vic_init(S3C_VA_VIC1, S3C_VIC1_BASE, vic1_valid, 0);
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/* add the timer sub-irqs */
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set_irq_chained_handler(IRQ_TIMER0_VIC, s3c_irq_demux_timer0);
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set_irq_chained_handler(IRQ_TIMER1_VIC, s3c_irq_demux_timer1);
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set_irq_chained_handler(IRQ_TIMER2_VIC, s3c_irq_demux_timer2);
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set_irq_chained_handler(IRQ_TIMER3_VIC, s3c_irq_demux_timer3);
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set_irq_chained_handler(IRQ_TIMER4_VIC, s3c_irq_demux_timer4);
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for (irq = IRQ_TIMER0; irq <= IRQ_TIMER4; irq++) {
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set_irq_chip(irq, &s3c_irq_timer);
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set_irq_handler(irq, handle_level_irq);
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set_irq_flags(irq, IRQF_VALID);
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}
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for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++)
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s3c64xx_uart_irq(&uart_irqs[uart]);
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}
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