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8bff82cbc3
Add w90p910 NAND driver for w90p910 evaluation board based on w90p910,there is a K8F1G08 NAND on my board. [dwmw2: depend on MTD_PARTITIONS] Signed-off-by: Wan ZongShun <mcuos.com@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
382 lines
8 KiB
C
382 lines
8 KiB
C
/*
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* Copyright (c) 2009 Nuvoton technology corporation.
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*
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* Wan ZongShun <mcuos.com@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation;version 2 of the License.
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*
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*/
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#define REG_FMICSR 0x00
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#define REG_SMCSR 0xa0
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#define REG_SMISR 0xac
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#define REG_SMCMD 0xb0
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#define REG_SMADDR 0xb4
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#define REG_SMDATA 0xb8
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#define RESET_FMI 0x01
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#define NAND_EN 0x08
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#define READYBUSY (0x01 << 18)
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#define SWRST 0x01
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#define PSIZE (0x01 << 3)
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#define DMARWEN (0x03 << 1)
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#define BUSWID (0x01 << 4)
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#define ECC4EN (0x01 << 5)
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#define WP (0x01 << 24)
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#define NANDCS (0x01 << 25)
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#define ENDADDR (0x01 << 31)
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#define read_data_reg(dev) \
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__raw_readl((dev)->reg + REG_SMDATA)
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#define write_data_reg(dev, val) \
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__raw_writel((val), (dev)->reg + REG_SMDATA)
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#define write_cmd_reg(dev, val) \
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__raw_writel((val), (dev)->reg + REG_SMCMD)
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#define write_addr_reg(dev, val) \
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__raw_writel((val), (dev)->reg + REG_SMADDR)
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struct w90p910_nand {
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struct mtd_info mtd;
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struct nand_chip chip;
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void __iomem *reg;
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struct clk *clk;
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spinlock_t lock;
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};
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static const struct mtd_partition partitions[] = {
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{
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.name = "NAND FS 0",
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.offset = 0,
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.size = 8 * 1024 * 1024
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},
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{
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.name = "NAND FS 1",
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.offset = MTDPART_OFS_APPEND,
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.size = MTDPART_SIZ_FULL
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}
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};
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static unsigned char w90p910_nand_read_byte(struct mtd_info *mtd)
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{
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unsigned char ret;
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struct w90p910_nand *nand;
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nand = container_of(mtd, struct w90p910_nand, mtd);
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ret = (unsigned char)read_data_reg(nand);
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return ret;
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}
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static void w90p910_nand_read_buf(struct mtd_info *mtd,
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unsigned char *buf, int len)
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{
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int i;
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struct w90p910_nand *nand;
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nand = container_of(mtd, struct w90p910_nand, mtd);
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for (i = 0; i < len; i++)
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buf[i] = (unsigned char)read_data_reg(nand);
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}
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static void w90p910_nand_write_buf(struct mtd_info *mtd,
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const unsigned char *buf, int len)
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{
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int i;
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struct w90p910_nand *nand;
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nand = container_of(mtd, struct w90p910_nand, mtd);
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for (i = 0; i < len; i++)
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write_data_reg(nand, buf[i]);
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}
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static int w90p910_verify_buf(struct mtd_info *mtd,
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const unsigned char *buf, int len)
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{
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int i;
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struct w90p910_nand *nand;
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nand = container_of(mtd, struct w90p910_nand, mtd);
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for (i = 0; i < len; i++) {
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if (buf[i] != (unsigned char)read_data_reg(nand))
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return -EFAULT;
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}
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return 0;
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}
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static int w90p910_check_rb(struct w90p910_nand *nand)
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{
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unsigned int val;
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spin_lock(&nand->lock);
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val = __raw_readl(REG_SMISR);
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val &= READYBUSY;
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spin_unlock(&nand->lock);
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return val;
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}
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static int w90p910_nand_devready(struct mtd_info *mtd)
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{
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struct w90p910_nand *nand;
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int ready;
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nand = container_of(mtd, struct w90p910_nand, mtd);
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ready = (w90p910_check_rb(nand)) ? 1 : 0;
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return ready;
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}
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static void w90p910_nand_command_lp(struct mtd_info *mtd,
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unsigned int command, int column, int page_addr)
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{
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register struct nand_chip *chip = mtd->priv;
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struct w90p910_nand *nand;
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nand = container_of(mtd, struct w90p910_nand, mtd);
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if (command == NAND_CMD_READOOB) {
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column += mtd->writesize;
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command = NAND_CMD_READ0;
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}
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write_cmd_reg(nand, command & 0xff);
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if (column != -1 || page_addr != -1) {
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if (column != -1) {
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if (chip->options & NAND_BUSWIDTH_16)
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column >>= 1;
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write_addr_reg(nand, column);
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write_addr_reg(nand, column >> 8 | ENDADDR);
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}
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if (page_addr != -1) {
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write_addr_reg(nand, page_addr);
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if (chip->chipsize > (128 << 20)) {
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write_addr_reg(nand, page_addr >> 8);
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write_addr_reg(nand, page_addr >> 16 | ENDADDR);
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} else {
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write_addr_reg(nand, page_addr >> 8 | ENDADDR);
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}
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}
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}
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switch (command) {
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case NAND_CMD_CACHEDPROG:
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case NAND_CMD_PAGEPROG:
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case NAND_CMD_ERASE1:
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case NAND_CMD_ERASE2:
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case NAND_CMD_SEQIN:
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case NAND_CMD_RNDIN:
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case NAND_CMD_STATUS:
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case NAND_CMD_DEPLETE1:
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return;
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case NAND_CMD_STATUS_ERROR:
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case NAND_CMD_STATUS_ERROR0:
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case NAND_CMD_STATUS_ERROR1:
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case NAND_CMD_STATUS_ERROR2:
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case NAND_CMD_STATUS_ERROR3:
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udelay(chip->chip_delay);
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return;
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case NAND_CMD_RESET:
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if (chip->dev_ready)
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break;
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udelay(chip->chip_delay);
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write_cmd_reg(nand, NAND_CMD_STATUS);
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write_cmd_reg(nand, command);
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while (!w90p910_check_rb(nand))
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;
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return;
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case NAND_CMD_RNDOUT:
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write_cmd_reg(nand, NAND_CMD_RNDOUTSTART);
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return;
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case NAND_CMD_READ0:
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write_cmd_reg(nand, NAND_CMD_READSTART);
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default:
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if (!chip->dev_ready) {
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udelay(chip->chip_delay);
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return;
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}
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}
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/* Apply this short delay always to ensure that we do wait tWB in
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* any case on any machine. */
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ndelay(100);
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while (!chip->dev_ready(mtd))
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;
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}
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static void w90p910_nand_enable(struct w90p910_nand *nand)
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{
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unsigned int val;
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spin_lock(&nand->lock);
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__raw_writel(RESET_FMI, (nand->reg + REG_FMICSR));
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val = __raw_readl(nand->reg + REG_FMICSR);
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if (!(val & NAND_EN))
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__raw_writel(val | NAND_EN, REG_FMICSR);
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val = __raw_readl(nand->reg + REG_SMCSR);
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val &= ~(SWRST|PSIZE|DMARWEN|BUSWID|ECC4EN|NANDCS);
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val |= WP;
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__raw_writel(val, nand->reg + REG_SMCSR);
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spin_unlock(&nand->lock);
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}
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static int __devinit w90p910_nand_probe(struct platform_device *pdev)
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{
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struct w90p910_nand *w90p910_nand;
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struct nand_chip *chip;
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int retval;
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struct resource *res;
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retval = 0;
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w90p910_nand = kzalloc(sizeof(struct w90p910_nand), GFP_KERNEL);
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if (!w90p910_nand)
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return -ENOMEM;
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chip = &(w90p910_nand->chip);
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w90p910_nand->mtd.priv = chip;
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w90p910_nand->mtd.owner = THIS_MODULE;
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spin_lock_init(&w90p910_nand->lock);
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w90p910_nand->clk = clk_get(&pdev->dev, NULL);
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if (IS_ERR(w90p910_nand->clk)) {
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retval = -ENOENT;
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goto fail1;
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}
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clk_enable(w90p910_nand->clk);
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chip->cmdfunc = w90p910_nand_command_lp;
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chip->dev_ready = w90p910_nand_devready;
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chip->read_byte = w90p910_nand_read_byte;
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chip->write_buf = w90p910_nand_write_buf;
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chip->read_buf = w90p910_nand_read_buf;
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chip->verify_buf = w90p910_verify_buf;
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chip->chip_delay = 50;
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chip->options = 0;
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chip->ecc.mode = NAND_ECC_SOFT;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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retval = -ENXIO;
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goto fail1;
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}
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if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
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retval = -EBUSY;
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goto fail1;
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}
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w90p910_nand->reg = ioremap(res->start, resource_size(res));
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if (!w90p910_nand->reg) {
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retval = -ENOMEM;
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goto fail2;
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}
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w90p910_nand_enable(w90p910_nand);
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if (nand_scan(&(w90p910_nand->mtd), 1)) {
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retval = -ENXIO;
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goto fail3;
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}
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add_mtd_partitions(&(w90p910_nand->mtd), partitions,
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ARRAY_SIZE(partitions));
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platform_set_drvdata(pdev, w90p910_nand);
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return retval;
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fail3: iounmap(w90p910_nand->reg);
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fail2: release_mem_region(res->start, resource_size(res));
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fail1: kfree(w90p910_nand);
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return retval;
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}
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static int __devexit w90p910_nand_remove(struct platform_device *pdev)
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{
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struct w90p910_nand *w90p910_nand = platform_get_drvdata(pdev);
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struct resource *res;
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iounmap(w90p910_nand->reg);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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release_mem_region(res->start, resource_size(res));
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clk_disable(w90p910_nand->clk);
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clk_put(w90p910_nand->clk);
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kfree(w90p910_nand);
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platform_set_drvdata(pdev, NULL);
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return 0;
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}
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static struct platform_driver w90p910_nand_driver = {
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.probe = w90p910_nand_probe,
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.remove = __devexit_p(w90p910_nand_remove),
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.driver = {
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.name = "w90p910-fmi",
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.owner = THIS_MODULE,
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},
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};
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static int __init w90p910_nand_init(void)
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{
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return platform_driver_register(&w90p910_nand_driver);
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}
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static void __exit w90p910_nand_exit(void)
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{
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platform_driver_unregister(&w90p910_nand_driver);
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}
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module_init(w90p910_nand_init);
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module_exit(w90p910_nand_exit);
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MODULE_AUTHOR("Wan ZongShun <mcuos.com@gmail.com>");
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MODULE_DESCRIPTION("w90p910 nand driver!");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:w90p910-fmi");
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