* 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-acpi-2.6: (34 commits)
classmate-laptop: add support for Classmate PC ACPI devices
hp-wmi: Fix two memleaks
acer-wmi, msi-wmi: Remove needless DMI MODULE_ALIAS
dell-wmi: do not keep driver loaded on unsupported boxes
wmi: Free the allocated acpi objects through wmi_get_event_data
drivers/platform/x86/acerhdf.c: check BIOS information whether it begins with string of table
acerhdf: add new BIOS versions
acerhdf: limit modalias matching to supported
toshiba_acpi: convert to seq_file
asus_acpi: convert to seq_file
ACPI: do not select ACPI_DOCK from ATA_ACPI
sony-laptop: enumerate rfkill devices using SN06
sony-laptop: rfkill support for newer models
ACPI: fix OSC regression that caused aer and pciehp not to load
MAINTAINERS: add maintainer for msi-wmi driver
fujitu-laptop: fix tests of acpi_evaluate_integer() return value
arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c: avoid cross-CPU interrupts by using smp_call_function_any()
ACPI: processor: remove _PDC object list from struct acpi_processor
ACPI: processor: change acpi_processor_set_pdc() interface
ACPI: processor: open code acpi_processor_cleanup_pdc
...
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm:
VIDEO: cyberpro: pci_request_regions needs a persistent name
ARM: dma-isa: request cascade channel after registering it
ARM: footbridge: trim down old ISA rtc setup
ARM: fix PAGE_KERNEL
ARM: Fix wrong shared bit for CPU write buffer bug test
ARM: 5857/1: ARM: dmabounce: fix build
ARM: 5856/1: Fix bug of uart0 platfrom data for nuc900
ARM: 5855/1: putc support for nuc900
ARM: 5854/1: fix compiling error for NUC900
ARM: 5849/1: ARMv7: fix Oprofile events count
ARM: add missing include to nwflash.c
ARM: Kill CONFIG_CPU_32
ARM: Convert VFP/Crunch/XscaleCP thread_release() to exit_thread()
ARM: 5853/1: ARM: Fix build break on ARM v6 and v7
This fixes a "start_kernel(): bug: interrupts were enabled early".
rtc_cmos now takes care of initializing the ISA RTC and reading the
current time and date from it; there's no need to repeat that here,
thereby causing interrupts to be enabled too early.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
PAGE_KERNEL should not be executable; any area marked executable can
be prefetched into the instruction cache. We don't want vmalloc areas
to be read in this way.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
With some of the cache rework an address aliasing optimization was added,
but this managed to fail on certain mappings resulting in pages with
PG_dcache_dirty set never writing back their dcache lines. This patch
reverts to the earlier behaviour of simply always writing back when the
dirty bit is set.
Signed-off-by: Markus Pietrek <Markus.Pietrek@emtrion.de>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
o remove unused define
o add device name comment
Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This reverts commit 9f15226e75. It's just
wrong, and broke resume for Rafael even on a non-AMD CPU.
As Rafael says:
"... it causes microcode_init_cpu() to be called during resume even for
CPUs for which there's no microcode to apply. That, in turn, results
in executing request_firmware() (on Intel CPUs at least) which doesn't
work at this stage of resume (we have device interrupts disabled, I/O
devices are still suspended and so on).
If I'm not mistaken, the "if (uci->valid)" logic means "if that CPU is
known to us" , so before commit 9f15226e75 microcode_resume_cpu() was
called for all CPUs already in the system during suspend, which was
the right thing to do. The commit changed it so that the CPUs without
microcode to apply are now treated as "unknown", which is not quite
right.
The problem this commit attempted to solve has to be handled
differently."
Bisected-and -requested-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
It is unpredictable to have the same memory mapped using different
shared bit settings for ARMv6 and ARMv7 CPUs. Fix this for the CPU
write buffer bug test.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (36 commits)
powerpc/gc/wii: Remove get_irq_desc()
powerpc/gc/wii: hlwd-pic: convert irq_desc.lock to raw_spinlock
powerpc/gamecube/wii: Fix off-by-one error in ugecon/usbgecko_udbg
powerpc/mpic: Fix problem that affinity is not updated
powerpc/mm: Fix stupid bug in subpge protection handling
powerpc/iseries: use DECLARE_COMPLETION_ONSTACK for non-constant completion
powerpc: Fix MSI support on U4 bridge PCIe slot
powerpc: Handle VSX alignment faults correctly in little-endian mode
powerpc/mm: Fix typo of cpumask_clear_cpu()
powerpc/mm: Fix hash_utils_64.c compile errors with DEBUG enabled.
powerpc: Convert BUG() to use unreachable()
powerpc/pseries: Make declarations of cpu_hotplug_driver_lock() ANSI compatible.
powerpc/pseries: Don't panic when H_PROD fails during cpu-online.
powerpc/mm: Fix a WARN_ON() with CONFIG_DEBUG_PAGEALLOC and CONFIG_DEBUG_VM
powerpc/defconfigs: Set HZ=100 on pseries and ppc64 defconfigs
powerpc/defconfigs: Disable token ring in powerpc defconfigs
powerpc/defconfigs: Reduce 64bit vmlinux by making acenic and cramfs modules
powerpc/pseries: Select XICS and PCI_MSI PSERIES
powerpc/85xx: Wrong variable returned on error
powerpc/iseries: Convert to proc_fops
...
Presently acpi-cpufreq will perform the MSR read on the first CPU in the
mask. That's inefficient if that CPU differs from the current CPU.
Because we have to perform a cross-CPU call, but we could have run the
rdmsr on the current CPU.
So switch to using the new smp_call_function_any(), which will perform the
call on the current CPU if that CPU is present in the mask (it is).
Cc: "Zhang, Yanmin" <yanmin_zhang@linux.intel.com>
Cc: Dave Jones <davej@redhat.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Jaswinder Singh Rajput <jaswinder@kernel.org>
Cc: Len Brown <len.brown@intel.com>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Rusty Russell <rusty@rustcorp.com.au>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Cc: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Len Brown <len.brown@intel.com>
Commit f74f7e57ae (ARM: use
flush_kernel_dcache_area() for dmabounce) has broken dmabounce build:
CC arch/arm/common/dmabounce.o
arch/arm/common/dmabounce.c: In function 'unmap_single':
arch/arm/common/dmabounce.c:315: error: implicit declaration of function '__cpuc_flush_kernel_dcache_area'
make[2]: *** [arch/arm/common/dmabounce.o] Error 1
Fix it.
Signed-off-by: Mike Rapoport <mike@compulab.co.il>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Fix bug of uart0 platfrom data for nuc900
Signed-off-by: lijie <eltshanli@gmail.com>
Signed-off-by: Wan ZongShun <mcuos.com@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
putc support for nuc900
Signed-off-by: lijie <eltshanli@gmail.com>
Signed-off-by: Wan ZongShun <mcuos.com@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
fix compiling error for NUC900
Signed-off-by: lijie <eltshanli@gmail.com>
Signed-off-by: Wan ZongShun <mcuos.com@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
On Oprofile ARMv7 the PMNC_D bit was set to lower the PMU IRQs
and so to decrease the risk of errata #628216 from appearing.
The effect of setting the PMNC_D bit is that the CCNT counter
is divided by 64, making the program counter events count
inaccurate.
The new OMAP3 r4 cores should have that errata fixed.
The PMNC_D bit should not be set, this patch fixes it.
Signed-off-by: Jean Pihet <jpihet@mvista.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The x86 and ia64 implementations of the function in $subject are
exactly the same.
Also, since the arch-specific implementations of setting _PDC have
been completely hollowed out, remove the empty shells.
Cc: Tony Luck <tony.luck@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Signed-off-by: Alex Chiang <achiang@hp.com>
Signed-off-by: Len Brown <len.brown@intel.com>
The only thing arch-specific about calling _PDC is what bits get
set in the input obj_list buffer.
There's no need for several levels of indirection to twiddle those
bits. Additionally, since we're just messing around with a buffer,
we can simplify the interface; no need to pass around the entire
struct acpi_processor * just to get at the buffer.
Cc: Tony Luck <tony.luck@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Signed-off-by: Alex Chiang <achiang@hp.com>
Signed-off-by: Len Brown <len.brown@intel.com>
Both x86 and ia64 initialize _PDC with mostly common bit settings.
Factor out the common settings and leave the arch-specific ones alone.
Cc: Tony Luck <tony.luck@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Signed-off-by: Alex Chiang <achiang@hp.com>
Signed-off-by: Len Brown <len.brown@intel.com>
The x86 and ia64 implementations of arch_acpi_processor_init_pdc()
are almost exactly the same. The only difference is in what bits
they set in obj_list buffer.
Combine the boilerplate memory management code, and leave the
arch-specific bit twiddling in separate implementations.
Cc: Tony Luck <tony.luck@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Signed-off-by: Alex Chiang <achiang@hp.com>
Signed-off-by: Len Brown <len.brown@intel.com>
arch dependent helper function that tells us if we should attempt to
evaluate _PDC on this machine or not.
The x86 implementation assumes that the CPUs in the machine must be
homogeneous, and that you cannot mix CPUs of different vendors.
Cc: Tony Luck <tony.luck@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Signed-off-by: Alex Chiang <achiang@hp.com>
Signed-off-by: Len Brown <len.brown@intel.com>
