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[ARM] 5537/1: Freescale STMP: 37nn registers definition
Add register definitions for Freescale STMP 37nn boards Signed-off-by: dmitry pervushin <dpervushin@embeddedalley.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
dmitry pervushin
Russell King
parent
98f420b23a
commit
fc3fdfd632
16 changed files with 1180 additions and 0 deletions
61
arch/arm/mach-stmp37xx/include/mach/regs-audioin.h
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61
arch/arm/mach-stmp37xx/include/mach/regs-audioin.h
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@ -0,0 +1,61 @@
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/*
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* stmp37xx: AUDIOIN register definitions
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*
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* Copyright (c) 2008 Freescale Semiconductor
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* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
|
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
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*
|
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* This program is distributed in the hope that it will be useful,
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||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#define REGS_AUDIOIN_BASE (STMP3XXX_REGS_BASE + 0x4C000)
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#define HW_AUDIOIN_CTRL 0x0
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#define BM_AUDIOIN_CTRL_RUN 0x00000001
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#define BP_AUDIOIN_CTRL_RUN 0
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#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
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#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
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#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
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#define BM_AUDIOIN_CTRL_WORD_LENGTH 0x00000020
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#define BM_AUDIOIN_CTRL_CLKGATE 0x40000000
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#define BM_AUDIOIN_CTRL_SFTRST 0x80000000
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#define HW_AUDIOIN_STAT 0x10
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#define HW_AUDIOIN_ADCSRR 0x20
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#define HW_AUDIOIN_ADCVOLUME 0x30
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#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0x000000FF
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#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0
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#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0x00FF0000
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#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16
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#define HW_AUDIOIN_ADCDEBUG 0x40
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#define HW_AUDIOIN_ADCVOL 0x50
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#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0x0000000F
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#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0
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#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x00000030
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#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 4
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#define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0x00000F00
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#define BP_AUDIOIN_ADCVOL_GAIN_LEFT 8
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#define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x00003000
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#define BP_AUDIOIN_ADCVOL_SELECT_LEFT 12
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#define BM_AUDIOIN_ADCVOL_MUTE 0x01000000
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#define HW_AUDIOIN_MICLINE 0x60
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#define HW_AUDIOIN_ANACLKCTRL 0x70
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#define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000
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#define HW_AUDIOIN_DATA 0x80
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111
arch/arm/mach-stmp37xx/include/mach/regs-audioout.h
Normal file
111
arch/arm/mach-stmp37xx/include/mach/regs-audioout.h
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@ -0,0 +1,111 @@
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/*
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* stmp37xx: AUDIOOUT register definitions
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*
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* Copyright (c) 2008 Freescale Semiconductor
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* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
|
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; either version 2 of the License, or
|
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#define REGS_AUDIOOUT_BASE (STMP3XXX_REGS_BASE + 0x48000)
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#define HW_AUDIOOUT_CTRL 0x0
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#define BM_AUDIOOUT_CTRL_RUN 0x00000001
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#define BP_AUDIOOUT_CTRL_RUN 0
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#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
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#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
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#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
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#define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x00000040
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#define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000
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#define BM_AUDIOOUT_CTRL_SFTRST 0x80000000
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#define HW_AUDIOOUT_STAT 0x10
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#define HW_AUDIOOUT_DACSRR 0x20
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#define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x00001FFF
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#define BP_AUDIOOUT_DACSRR_SRC_FRAC 0
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#define BM_AUDIOOUT_DACSRR_SRC_INT 0x001F0000
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#define BP_AUDIOOUT_DACSRR_SRC_INT 16
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#define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x07000000
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#define BP_AUDIOOUT_DACSRR_SRC_HOLD 24
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#define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000
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#define BP_AUDIOOUT_DACSRR_BASEMULT 28
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#define HW_AUDIOOUT_DACVOLUME 0x30
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#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x00000100
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#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x01000000
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#define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x02000000
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#define HW_AUDIOOUT_DACDEBUG 0x40
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#define HW_AUDIOOUT_HPVOL 0x50
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#define BM_AUDIOOUT_HPVOL_MUTE 0x01000000
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#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD 0x02000000
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#define HW_AUDIOOUT_PWRDN 0x70
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#define BM_AUDIOOUT_PWRDN_HEADPHONE 0x00000001
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#define BP_AUDIOOUT_PWRDN_HEADPHONE 0
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#define BM_AUDIOOUT_PWRDN_CAPLESS 0x00000010
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#define BM_AUDIOOUT_PWRDN_ADC 0x00000100
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#define BM_AUDIOOUT_PWRDN_DAC 0x00001000
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#define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x00010000
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#define BM_AUDIOOUT_PWRDN_LINEOUT 0x01000000
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#define HW_AUDIOOUT_REFCTRL 0x80
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#define BM_AUDIOOUT_REFCTRL_VAG_VAL 0x000000F0
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#define BP_AUDIOOUT_REFCTRL_VAG_VAL 4
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#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0x00000F00
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#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8
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#define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x00001000
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#define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x00002000
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#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x00030000
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#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16
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#define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x00080000
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#define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x00700000
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#define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20
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#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x01000000
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#define BM_AUDIOOUT_REFCTRL_RAISE_REF 0x02000000
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#define HW_AUDIOOUT_ANACTRL 0x90
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#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x00000010
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#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x00000020
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#define HW_AUDIOOUT_TEST 0xA0
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#define BM_AUDIOOUT_TEST_HP_I1_ADJ 0x00C00000
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#define BP_AUDIOOUT_TEST_HP_I1_ADJ 22
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#define HW_AUDIOOUT_BISTCTRL 0xB0
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#define HW_AUDIOOUT_BISTSTAT0 0xC0
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#define HW_AUDIOOUT_BISTSTAT1 0xD0
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#define HW_AUDIOOUT_ANACLKCTRL 0xE0
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#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE 0x80000000
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#define HW_AUDIOOUT_DATA 0xF0
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#define HW_AUDIOOUT_LINEOUTCTRL 0x100
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#define BM_AUDIOOUT_LINEOUTCTRL_VOL_RIGHT 0x0000001F
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#define BP_AUDIOOUT_LINEOUTCTRL_VOL_RIGHT 0
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#define BM_AUDIOOUT_LINEOUTCTRL_VOL_LEFT 0x00001F00
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#define BP_AUDIOOUT_LINEOUTCTRL_VOL_LEFT 8
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#define BM_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP 0x00007000
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#define BP_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP 12
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#define BM_AUDIOOUT_LINEOUTCTRL_VAG_CTRL 0x00F00000
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#define BP_AUDIOOUT_LINEOUTCTRL_VAG_CTRL 20
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#define BM_AUDIOOUT_LINEOUTCTRL_MUTE 0x01000000
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#define BM_AUDIOOUT_LINEOUTCTRL_EN_ZCD 0x02000000
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#define HW_AUDIOOUT_VERSION 0x200
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24
arch/arm/mach-stmp37xx/include/mach/regs-digctl.h
Normal file
24
arch/arm/mach-stmp37xx/include/mach/regs-digctl.h
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@ -0,0 +1,24 @@
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/*
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* stmp37xx: DIGCTL register definitions
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*
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* Copyright (c) 2008 Freescale Semiconductor
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* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
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*
|
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* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#define REGS_DIGCTL_BASE (STMP3XXX_REGS_BASE + 0x1C000)
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#define HW_DIGCTL_CTRL 0x0
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#define BM_DIGCTL_CTRL_USB_CLKGATE 0x00000004
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37
arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h
Normal file
37
arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h
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@ -0,0 +1,37 @@
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/*
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* stmp37xx: ECC8 register definitions
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*
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* Copyright (c) 2008 Freescale Semiconductor
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* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; either version 2 of the License, or
|
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
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*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#define REGS_ECC8_BASE (STMP3XXX_REGS_BASE + 0x8000)
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#define HW_ECC8_CTRL 0x0
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#define BM_ECC8_CTRL_COMPLETE_IRQ 0x00000001
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#define BP_ECC8_CTRL_COMPLETE_IRQ 0
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#define BM_ECC8_CTRL_COMPLETE_IRQ_EN 0x00000100
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#define BM_ECC8_CTRL_AHBM_SFTRST 0x20000000
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#define HW_ECC8_STATUS0 0x10
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#define BM_ECC8_STATUS0_UNCORRECTABLE 0x00000004
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#define BM_ECC8_STATUS0_CORRECTED 0x00000008
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#define BM_ECC8_STATUS0_STATUS_AUX 0x00000F00
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#define BP_ECC8_STATUS0_STATUS_AUX 8
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#define BM_ECC8_STATUS0_COMPLETED_CE 0x000F0000
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#define BP_ECC8_STATUS0_COMPLETED_CE 16
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#define HW_ECC8_STATUS1 0x20
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63
arch/arm/mach-stmp37xx/include/mach/regs-gpmi.h
Normal file
63
arch/arm/mach-stmp37xx/include/mach/regs-gpmi.h
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@ -0,0 +1,63 @@
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/*
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* stmp37xx: GPMI register definitions
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*
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* Copyright (c) 2008 Freescale Semiconductor
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* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#define REGS_GPMI_BASE (STMP3XXX_REGS_BASE + 0xC000)
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#define REGS_GPMI_PHYS 0x8000C000
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#define REGS_GPMI_SIZE 0x2000
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#define HW_GPMI_CTRL0 0x0
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#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF
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#define BP_GPMI_CTRL0_XFER_COUNT 0
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#define BM_GPMI_CTRL0_CS 0x00300000
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#define BP_GPMI_CTRL0_CS 20
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#define BM_GPMI_CTRL0_LOCK_CS 0x00400000
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#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000
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#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000
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#define BP_GPMI_CTRL0_COMMAND_MODE 24
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#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0
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#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1
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#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
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#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3
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#define BM_GPMI_CTRL0_RUN 0x20000000
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#define BM_GPMI_CTRL0_CLKGATE 0x40000000
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#define BM_GPMI_CTRL0_SFTRST 0x80000000
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#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000
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#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000
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#define BP_GPMI_ECCCTRL_ECC_CMD 13
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#define HW_GPMI_CTRL1 0x60
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#define BM_GPMI_CTRL1_GPMI_MODE 0x00000003
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#define BP_GPMI_CTRL1_GPMI_MODE 0
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#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004
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#define BM_GPMI_CTRL1_DEV_RESET 0x00000008
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#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200
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#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400
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#define BM_GPMI_CTRL1_DSAMPLE_TIME 0x00007000
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#define BP_GPMI_CTRL1_DSAMPLE_TIME 12
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#define HW_GPMI_TIMING0 0x70
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#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF
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#define BP_GPMI_TIMING0_DATA_SETUP 0
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#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00
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#define BP_GPMI_TIMING0_DATA_HOLD 8
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#define HW_GPMI_TIMING1 0x80
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#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000
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#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16
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55
arch/arm/mach-stmp37xx/include/mach/regs-i2c.h
Normal file
55
arch/arm/mach-stmp37xx/include/mach/regs-i2c.h
Normal file
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@ -0,0 +1,55 @@
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/*
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* stmp37xx: I2C register definitions
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*
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* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
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#define REGS_I2C_BASE (STMP3XXX_REGS_BASE + 0x58000)
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#define REGS_I2C_PHYS 0x80058000
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#define REGS_I2C_SIZE 0x2000
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#define HW_I2C_CTRL0 0x0
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#define BM_I2C_CTRL0_XFER_COUNT 0x0000FFFF
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#define BP_I2C_CTRL0_XFER_COUNT 0
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#define BM_I2C_CTRL0_DIRECTION 0x00010000
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#define BM_I2C_CTRL0_MASTER_MODE 0x00020000
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#define BM_I2C_CTRL0_PRE_SEND_START 0x00080000
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#define BM_I2C_CTRL0_POST_SEND_STOP 0x00100000
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#define BM_I2C_CTRL0_RETAIN_CLOCK 0x00200000
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#define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000
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#define BM_I2C_CTRL0_CLKGATE 0x40000000
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#define BM_I2C_CTRL0_SFTRST 0x80000000
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#define HW_I2C_TIMING0 0x10
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#define HW_I2C_TIMING1 0x20
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#define HW_I2C_TIMING2 0x30
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#define HW_I2C_CTRL1 0x40
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#define BM_I2C_CTRL1_SLAVE_IRQ 0x00000001
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#define BP_I2C_CTRL1_SLAVE_IRQ 0
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#define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x00000002
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#define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x00000004
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#define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x00000008
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#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x00000010
|
||||
#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x00000020
|
||||
#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x00000040
|
||||
#define BM_I2C_CTRL1_BUS_FREE_IRQ 0x00000080
|
||||
#define BM_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000
|
||||
|
||||
#define HW_I2C_VERSION 0x90
|
||||
89
arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h
Normal file
89
arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h
Normal file
|
|
@ -0,0 +1,89 @@
|
|||
/*
|
||||
* stmp37xx: LCDIF register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_LCDIF_BASE (STMP3XXX_REGS_BASE + 0x30000)
|
||||
#define REGS_LCDIF_PHYS 0x80030000
|
||||
#define REGS_LCDIF_SIZE 0x2000
|
||||
|
||||
#define HW_LCDIF_CTRL 0x0
|
||||
#define BM_LCDIF_CTRL_COUNT 0x0000FFFF
|
||||
#define BP_LCDIF_CTRL_COUNT 0
|
||||
#define BM_LCDIF_CTRL_RUN 0x00010000
|
||||
#define BM_LCDIF_CTRL_WORD_LENGTH 0x00020000
|
||||
#define BM_LCDIF_CTRL_DATA_SELECT 0x00040000
|
||||
#define BM_LCDIF_CTRL_DOTCLK_MODE 0x00080000
|
||||
#define BM_LCDIF_CTRL_VSYNC_MODE 0x00100000
|
||||
#define BM_LCDIF_CTRL_DATA_SWIZZLE 0x00600000
|
||||
#define BP_LCDIF_CTRL_DATA_SWIZZLE 21
|
||||
#define BM_LCDIF_CTRL_BYPASS_COUNT 0x00800000
|
||||
#define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x06000000
|
||||
#define BP_LCDIF_CTRL_SHIFT_NUM_BITS 25
|
||||
#define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x08000000
|
||||
#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x10000000
|
||||
#define BM_LCDIF_CTRL_CLKGATE 0x40000000
|
||||
#define BM_LCDIF_CTRL_SFTRST 0x80000000
|
||||
|
||||
#define HW_LCDIF_CTRL1 0x10
|
||||
#define BM_LCDIF_CTRL1_RESET 0x00000001
|
||||
#define BP_LCDIF_CTRL1_RESET 0
|
||||
#define BM_LCDIF_CTRL1_MODE86 0x00000002
|
||||
#define BM_LCDIF_CTRL1_BUSY_ENABLE 0x00000004
|
||||
#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100
|
||||
#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200
|
||||
#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400
|
||||
#define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x00000800
|
||||
#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000
|
||||
#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000
|
||||
#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16
|
||||
|
||||
#define HW_LCDIF_TIMING 0x20
|
||||
|
||||
#define HW_LCDIF_VDCTRL0 0x30
|
||||
#define BM_LCDIF_VDCTRL0_VALID_DATA_CNT 0x000003FF
|
||||
#define BP_LCDIF_VDCTRL0_VALID_DATA_CNT 0
|
||||
#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000
|
||||
#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000
|
||||
#define BM_LCDIF_VDCTRL0_ENABLE_POL 0x01000000
|
||||
#define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x02000000
|
||||
#define BM_LCDIF_VDCTRL0_HSYNC_POL 0x04000000
|
||||
#define BM_LCDIF_VDCTRL0_VSYNC_POL 0x08000000
|
||||
#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000
|
||||
#define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000
|
||||
|
||||
#define HW_LCDIF_VDCTRL1 0x40
|
||||
#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0x000FFFFF
|
||||
#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0
|
||||
#define BM_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH 0xFFF00000
|
||||
#define BP_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH 20
|
||||
|
||||
#define HW_LCDIF_VDCTRL2 0x50
|
||||
#define BM_LCDIF_VDCTRL2_VALID_DATA_CNT 0x000007FF
|
||||
#define BP_LCDIF_VDCTRL2_VALID_DATA_CNT 0
|
||||
#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x007FF800
|
||||
#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 11
|
||||
#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFF800000
|
||||
#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 23
|
||||
|
||||
#define HW_LCDIF_VDCTRL3 0x60
|
||||
#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x000001FF
|
||||
#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0
|
||||
#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x00FFF000
|
||||
#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 12
|
||||
#define BM_LCDIF_VDCTRL3_SYNC_SIGNALS_ON 0x01000000
|
||||
97
arch/arm/mach-stmp37xx/include/mach/regs-lradc.h
Normal file
97
arch/arm/mach-stmp37xx/include/mach/regs-lradc.h
Normal file
|
|
@ -0,0 +1,97 @@
|
|||
/*
|
||||
* stmp37xx: LRADC register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_LRADC_BASE (STMP3XXX_REGS_BASE + 0x50000)
|
||||
|
||||
#define HW_LRADC_CTRL0 0x0
|
||||
#define BM_LRADC_CTRL0_SCHEDULE 0x000000FF
|
||||
#define BP_LRADC_CTRL0_SCHEDULE 0
|
||||
#define BM_LRADC_CTRL0_XPLUS_ENABLE 0x00010000
|
||||
#define BM_LRADC_CTRL0_YPLUS_ENABLE 0x00020000
|
||||
#define BM_LRADC_CTRL0_XMINUS_ENABLE 0x00040000
|
||||
#define BM_LRADC_CTRL0_YMINUS_ENABLE 0x00080000
|
||||
#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x00100000
|
||||
#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x00200000
|
||||
#define BM_LRADC_CTRL0_CLKGATE 0x40000000
|
||||
#define BM_LRADC_CTRL0_SFTRST 0x80000000
|
||||
|
||||
#define HW_LRADC_CTRL1 0x10
|
||||
#define BM_LRADC_CTRL1_LRADC0_IRQ 0x00000001
|
||||
#define BP_LRADC_CTRL1_LRADC0_IRQ 0
|
||||
#define BM_LRADC_CTRL1_LRADC5_IRQ 0x00000020
|
||||
#define BM_LRADC_CTRL1_LRADC6_IRQ 0x00000040
|
||||
#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x00000100
|
||||
#define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x00010000
|
||||
#define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x00200000
|
||||
#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x01000000
|
||||
|
||||
#define HW_LRADC_CTRL2 0x20
|
||||
#define BM_LRADC_CTRL2_BL_BRIGHTNESS 0x001F0000
|
||||
#define BP_LRADC_CTRL2_BL_BRIGHTNESS 16
|
||||
#define BM_LRADC_CTRL2_BL_MUX_SELECT 0x00200000
|
||||
#define BM_LRADC_CTRL2_BL_ENABLE 0x00400000
|
||||
#define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xFF000000
|
||||
#define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24
|
||||
|
||||
#define HW_LRADC_CTRL3 0x30
|
||||
#define BM_LRADC_CTRL3_CYCLE_TIME 0x00000300
|
||||
#define BP_LRADC_CTRL3_CYCLE_TIME 8
|
||||
|
||||
#define HW_LRADC_STATUS 0x40
|
||||
#define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x00000001
|
||||
#define BP_LRADC_STATUS_TOUCH_DETECT_RAW 0
|
||||
|
||||
#define HW_LRADC_CH0 (0x50 + 0 * 0x10)
|
||||
#define HW_LRADC_CH1 (0x50 + 1 * 0x10)
|
||||
#define HW_LRADC_CH2 (0x50 + 2 * 0x10)
|
||||
#define HW_LRADC_CH3 (0x50 + 3 * 0x10)
|
||||
#define HW_LRADC_CH4 (0x50 + 4 * 0x10)
|
||||
#define HW_LRADC_CH5 (0x50 + 5 * 0x10)
|
||||
#define HW_LRADC_CH6 (0x50 + 6 * 0x10)
|
||||
#define HW_LRADC_CH7 (0x50 + 7 * 0x10)
|
||||
|
||||
#define HW_LRADC_CHn 0x50
|
||||
#define BM_LRADC_CHn_VALUE 0x0003FFFF
|
||||
#define BP_LRADC_CHn_VALUE 0
|
||||
#define BM_LRADC_CHn_NUM_SAMPLES 0x1F000000
|
||||
#define BP_LRADC_CHn_NUM_SAMPLES 24
|
||||
#define BM_LRADC_CHn_ACCUMULATE 0x20000000
|
||||
|
||||
#define HW_LRADC_DELAY0 (0xD0 + 0 * 0x10)
|
||||
#define HW_LRADC_DELAY1 (0xD0 + 1 * 0x10)
|
||||
#define HW_LRADC_DELAY2 (0xD0 + 2 * 0x10)
|
||||
#define HW_LRADC_DELAY3 (0xD0 + 3 * 0x10)
|
||||
|
||||
#define HW_LRADC_DELAYn 0xD0
|
||||
#define BM_LRADC_DELAYn_DELAY 0x000007FF
|
||||
#define BP_LRADC_DELAYn_DELAY 0
|
||||
#define BM_LRADC_DELAYn_LOOP_COUNT 0x0000F800
|
||||
#define BP_LRADC_DELAYn_LOOP_COUNT 11
|
||||
#define BM_LRADC_DELAYn_TRIGGER_DELAYS 0x000F0000
|
||||
#define BP_LRADC_DELAYn_TRIGGER_DELAYS 16
|
||||
#define BM_LRADC_DELAYn_KICK 0x00100000
|
||||
#define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xFF000000
|
||||
#define BP_LRADC_DELAYn_TRIGGER_LRADCS 24
|
||||
|
||||
#define HW_LRADC_CTRL4 0x140
|
||||
#define BM_LRADC_CTRL4_LRADC6SELECT 0x0F000000
|
||||
#define BP_LRADC_CTRL4_LRADC6SELECT 24
|
||||
#define BM_LRADC_CTRL4_LRADC7SELECT 0xF0000000
|
||||
#define BP_LRADC_CTRL4_LRADC7SELECT 28
|
||||
51
arch/arm/mach-stmp37xx/include/mach/regs-pwm.h
Normal file
51
arch/arm/mach-stmp37xx/include/mach/regs-pwm.h
Normal file
|
|
@ -0,0 +1,51 @@
|
|||
/*
|
||||
* stmp37xx: PWM register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_PWM_BASE (STMP3XXX_REGS_BASE + 0x64000)
|
||||
|
||||
#define HW_PWM_CTRL 0x0
|
||||
#define BM_PWM_CTRL_PWM2_ENABLE 0x00000004
|
||||
#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE 0x00000020
|
||||
|
||||
#define HW_PWM_ACTIVE0 (0x10 + 0 * 0x20)
|
||||
#define HW_PWM_ACTIVE1 (0x10 + 1 * 0x20)
|
||||
#define HW_PWM_ACTIVE2 (0x10 + 2 * 0x20)
|
||||
#define HW_PWM_ACTIVE3 (0x10 + 3 * 0x20)
|
||||
|
||||
#define HW_PWM_ACTIVEn 0x10
|
||||
#define BM_PWM_ACTIVEn_ACTIVE 0x0000FFFF
|
||||
#define BP_PWM_ACTIVEn_ACTIVE 0
|
||||
#define BM_PWM_ACTIVEn_INACTIVE 0xFFFF0000
|
||||
#define BP_PWM_ACTIVEn_INACTIVE 16
|
||||
|
||||
#define HW_PWM_PERIOD0 (0x20 + 0 * 0x20)
|
||||
#define HW_PWM_PERIOD1 (0x20 + 1 * 0x20)
|
||||
#define HW_PWM_PERIOD2 (0x20 + 2 * 0x20)
|
||||
#define HW_PWM_PERIOD3 (0x20 + 3 * 0x20)
|
||||
|
||||
#define HW_PWM_PERIODn 0x20
|
||||
#define BM_PWM_PERIODn_PERIOD 0x0000FFFF
|
||||
#define BP_PWM_PERIODn_PERIOD 0
|
||||
#define BM_PWM_PERIODn_ACTIVE_STATE 0x00030000
|
||||
#define BP_PWM_PERIODn_ACTIVE_STATE 16
|
||||
#define BM_PWM_PERIODn_INACTIVE_STATE 0x000C0000
|
||||
#define BP_PWM_PERIODn_INACTIVE_STATE 18
|
||||
#define BM_PWM_PERIODn_CDIV 0x00700000
|
||||
#define BP_PWM_PERIODn_CDIV 20
|
||||
57
arch/arm/mach-stmp37xx/include/mach/regs-rtc.h
Normal file
57
arch/arm/mach-stmp37xx/include/mach/regs-rtc.h
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* stmp37xx: RTC register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_RTC_BASE (STMP3XXX_REGS_BASE + 0x5C000)
|
||||
#define REGS_RTC_PHYS 0x8005C000
|
||||
#define REGS_RTC_SIZE 0x2000
|
||||
|
||||
#define HW_RTC_CTRL 0x0
|
||||
#define BM_RTC_CTRL_ALARM_IRQ_EN 0x00000001
|
||||
#define BP_RTC_CTRL_ALARM_IRQ_EN 0
|
||||
#define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002
|
||||
#define BM_RTC_CTRL_ALARM_IRQ 0x00000004
|
||||
#define BM_RTC_CTRL_ONEMSEC_IRQ 0x00000008
|
||||
#define BM_RTC_CTRL_WATCHDOGEN 0x00000010
|
||||
|
||||
#define HW_RTC_STAT 0x10
|
||||
#define BM_RTC_STAT_NEW_REGS 0x0000FF00
|
||||
#define BP_RTC_STAT_NEW_REGS 8
|
||||
#define BM_RTC_STAT_STALE_REGS 0x00FF0000
|
||||
#define BP_RTC_STAT_STALE_REGS 16
|
||||
#define BM_RTC_STAT_RTC_PRESENT 0x80000000
|
||||
|
||||
#define HW_RTC_SECONDS 0x30
|
||||
|
||||
#define HW_RTC_ALARM 0x40
|
||||
|
||||
#define HW_RTC_WATCHDOG 0x50
|
||||
|
||||
#define HW_RTC_PERSISTENT0 0x60
|
||||
#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x00000002
|
||||
#define BM_RTC_PERSISTENT0_ALARM_EN 0x00000004
|
||||
#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 0x00000010
|
||||
#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 0x00000020
|
||||
#define BM_RTC_PERSISTENT0_ALARM_WAKE 0x00000080
|
||||
#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xFFFC0000
|
||||
#define BP_RTC_PERSISTENT0_SPARE_ANALOG 18
|
||||
|
||||
#define HW_RTC_PERSISTENT1 0x70
|
||||
|
||||
#define HW_RTC_VERSION 0xD0
|
||||
101
arch/arm/mach-stmp37xx/include/mach/regs-ssp.h
Normal file
101
arch/arm/mach-stmp37xx/include/mach/regs-ssp.h
Normal file
|
|
@ -0,0 +1,101 @@
|
|||
/*
|
||||
* stmp37xx: SSP register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_SSP_BASE (STMP3XXX_REGS_BASE + 0x10000)
|
||||
#define REGS_SSP1_PHYS 0x80010000
|
||||
#define REGS_SSP2_PHYS 0x80034000
|
||||
#define REGS_SSP_SIZE 0x2000
|
||||
|
||||
#define HW_SSP_CTRL0 0x0
|
||||
#define BM_SSP_CTRL0_XFER_COUNT 0x0000FFFF
|
||||
#define BP_SSP_CTRL0_XFER_COUNT 0
|
||||
#define BM_SSP_CTRL0_ENABLE 0x00010000
|
||||
#define BM_SSP_CTRL0_GET_RESP 0x00020000
|
||||
#define BM_SSP_CTRL0_LONG_RESP 0x00080000
|
||||
#define BM_SSP_CTRL0_WAIT_FOR_CMD 0x00100000
|
||||
#define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x00200000
|
||||
#define BM_SSP_CTRL0_BUS_WIDTH 0x00C00000
|
||||
#define BP_SSP_CTRL0_BUS_WIDTH 22
|
||||
#define BM_SSP_CTRL0_DATA_XFER 0x01000000
|
||||
#define BM_SSP_CTRL0_READ 0x02000000
|
||||
#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000
|
||||
#define BM_SSP_CTRL0_LOCK_CS 0x08000000
|
||||
#define BM_SSP_CTRL0_RUN 0x20000000
|
||||
#define BM_SSP_CTRL0_CLKGATE 0x40000000
|
||||
#define BM_SSP_CTRL0_SFTRST 0x80000000
|
||||
|
||||
#define HW_SSP_CMD0 0x10
|
||||
#define BM_SSP_CMD0_CMD 0x000000FF
|
||||
#define BP_SSP_CMD0_CMD 0
|
||||
#define BM_SSP_CMD0_BLOCK_COUNT 0x0000FF00
|
||||
#define BP_SSP_CMD0_BLOCK_COUNT 8
|
||||
#define BM_SSP_CMD0_BLOCK_SIZE 0x000F0000
|
||||
#define BP_SSP_CMD0_BLOCK_SIZE 16
|
||||
#define BM_SSP_CMD0_APPEND_8CYC 0x00100000
|
||||
#define BM_SSP_CMD1_CMD_ARG 0xFFFFFFFF
|
||||
#define BP_SSP_CMD1_CMD_ARG 0
|
||||
|
||||
#define HW_SSP_TIMING 0x50
|
||||
#define BM_SSP_TIMING_CLOCK_RATE 0x000000FF
|
||||
#define BP_SSP_TIMING_CLOCK_RATE 0
|
||||
#define BM_SSP_TIMING_CLOCK_DIVIDE 0x0000FF00
|
||||
#define BP_SSP_TIMING_CLOCK_DIVIDE 8
|
||||
#define BM_SSP_TIMING_TIMEOUT 0xFFFF0000
|
||||
#define BP_SSP_TIMING_TIMEOUT 16
|
||||
|
||||
#define HW_SSP_CTRL1 0x60
|
||||
#define BM_SSP_CTRL1_SSP_MODE 0x0000000F
|
||||
#define BP_SSP_CTRL1_SSP_MODE 0
|
||||
#define BM_SSP_CTRL1_WORD_LENGTH 0x000000F0
|
||||
#define BP_SSP_CTRL1_WORD_LENGTH 4
|
||||
#define BM_SSP_CTRL1_POLARITY 0x00000200
|
||||
#define BM_SSP_CTRL1_PHASE 0x00000400
|
||||
#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000
|
||||
#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x00008000
|
||||
#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x00010000
|
||||
#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x00020000
|
||||
#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x00200000
|
||||
#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x00400000
|
||||
#define BM_SSP_CTRL1_DATA_CRC_IRQ 0x00800000
|
||||
#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x01000000
|
||||
#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x02000000
|
||||
#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x04000000
|
||||
#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x08000000
|
||||
#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000
|
||||
#define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000
|
||||
#define BM_SSP_CTRL1_SDIO_IRQ 0x80000000
|
||||
|
||||
#define HW_SSP_DATA 0x70
|
||||
|
||||
#define HW_SSP_SDRESP0 0x80
|
||||
|
||||
#define HW_SSP_SDRESP1 0x90
|
||||
|
||||
#define HW_SSP_SDRESP2 0xA0
|
||||
|
||||
#define HW_SSP_SDRESP3 0xB0
|
||||
|
||||
#define HW_SSP_STATUS 0xC0
|
||||
#define BM_SSP_STATUS_FIFO_EMPTY 0x00000020
|
||||
#define BM_SSP_STATUS_TIMEOUT 0x00001000
|
||||
#define BM_SSP_STATUS_RESP_TIMEOUT 0x00004000
|
||||
#define BM_SSP_STATUS_RESP_ERR 0x00008000
|
||||
#define BM_SSP_STATUS_RESP_CRC_ERR 0x00010000
|
||||
#define BM_SSP_STATUS_CARD_DETECT 0x10000000
|
||||
85
arch/arm/mach-stmp37xx/include/mach/regs-uartapp.h
Normal file
85
arch/arm/mach-stmp37xx/include/mach/regs-uartapp.h
Normal file
|
|
@ -0,0 +1,85 @@
|
|||
/*
|
||||
* stmp37xx: UARTAPP register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_UARTAPP_BASE (STMP3XXX_REGS_BASE + 0x6C000)
|
||||
#define REGS_UARTAPP1_PHYS 0x8006C000
|
||||
#define REGS_UARTAPP_SIZE 0x2000
|
||||
|
||||
#define HW_UARTAPP_CTRL0 0x0
|
||||
#define BM_UARTAPP_CTRL0_XFER_COUNT 0x0000FFFF
|
||||
#define BP_UARTAPP_CTRL0_XFER_COUNT 0
|
||||
#define BM_UARTAPP_CTRL0_RXTIMEOUT 0x07FF0000
|
||||
#define BP_UARTAPP_CTRL0_RXTIMEOUT 16
|
||||
#define BM_UARTAPP_CTRL0_RXTO_ENABLE 0x08000000
|
||||
#define BM_UARTAPP_CTRL0_RUN 0x20000000
|
||||
#define BM_UARTAPP_CTRL0_SFTRST 0x80000000
|
||||
#define BM_UARTAPP_CTRL1_XFER_COUNT 0x0000FFFF
|
||||
#define BP_UARTAPP_CTRL1_XFER_COUNT 0
|
||||
#define BM_UARTAPP_CTRL1_RUN 0x10000000
|
||||
|
||||
#define HW_UARTAPP_CTRL2 0x20
|
||||
#define BM_UARTAPP_CTRL2_UARTEN 0x00000001
|
||||
#define BP_UARTAPP_CTRL2_UARTEN 0
|
||||
#define BM_UARTAPP_CTRL2_TXE 0x00000100
|
||||
#define BM_UARTAPP_CTRL2_RXE 0x00000200
|
||||
#define BM_UARTAPP_CTRL2_RTS 0x00000800
|
||||
#define BM_UARTAPP_CTRL2_RTSEN 0x00004000
|
||||
#define BM_UARTAPP_CTRL2_CTSEN 0x00008000
|
||||
#define BM_UARTAPP_CTRL2_RXDMAE 0x01000000
|
||||
#define BM_UARTAPP_CTRL2_TXDMAE 0x02000000
|
||||
#define BM_UARTAPP_CTRL2_DMAONERR 0x04000000
|
||||
|
||||
#define HW_UARTAPP_LINECTRL 0x30
|
||||
#define BM_UARTAPP_LINECTRL_BRK 0x00000001
|
||||
#define BP_UARTAPP_LINECTRL_BRK 0
|
||||
#define BM_UARTAPP_LINECTRL_PEN 0x00000002
|
||||
#define BM_UARTAPP_LINECTRL_EPS 0x00000004
|
||||
#define BM_UARTAPP_LINECTRL_STP2 0x00000008
|
||||
#define BM_UARTAPP_LINECTRL_FEN 0x00000010
|
||||
#define BM_UARTAPP_LINECTRL_WLEN 0x00000060
|
||||
#define BP_UARTAPP_LINECTRL_WLEN 5
|
||||
#define BM_UARTAPP_LINECTRL_SPS 0x00000080
|
||||
#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC 0x00003F00
|
||||
#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC 8
|
||||
#define BM_UARTAPP_LINECTRL_BAUD_DIVINT 0xFFFF0000
|
||||
#define BP_UARTAPP_LINECTRL_BAUD_DIVINT 16
|
||||
|
||||
#define HW_UARTAPP_INTR 0x50
|
||||
#define BM_UARTAPP_INTR_CTSMIS 0x00000002
|
||||
#define BM_UARTAPP_INTR_RTIS 0x00000040
|
||||
#define BM_UARTAPP_INTR_CTSMIEN 0x00020000
|
||||
#define BM_UARTAPP_INTR_RXIEN 0x00100000
|
||||
#define BM_UARTAPP_INTR_RTIEN 0x00400000
|
||||
|
||||
#define HW_UARTAPP_DATA 0x60
|
||||
|
||||
#define HW_UARTAPP_STAT 0x70
|
||||
#define BM_UARTAPP_STAT_RXCOUNT 0x0000FFFF
|
||||
#define BP_UARTAPP_STAT_RXCOUNT 0
|
||||
#define BM_UARTAPP_STAT_FERR 0x00010000
|
||||
#define BM_UARTAPP_STAT_PERR 0x00020000
|
||||
#define BM_UARTAPP_STAT_BERR 0x00040000
|
||||
#define BM_UARTAPP_STAT_OERR 0x00080000
|
||||
#define BM_UARTAPP_STAT_RXFE 0x01000000
|
||||
#define BM_UARTAPP_STAT_TXFF 0x02000000
|
||||
#define BM_UARTAPP_STAT_TXFE 0x08000000
|
||||
#define BM_UARTAPP_STAT_CTS 0x10000000
|
||||
|
||||
#define HW_UARTAPP_VERSION 0x90
|
||||
268
arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h
Normal file
268
arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h
Normal file
|
|
@ -0,0 +1,268 @@
|
|||
/*
|
||||
* stmp378x: UARTDBG register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_UARTDBG_BASE (STMP3XXX_REGS_BASE + 0x70000)
|
||||
#define REGS_UARTDBG_PHYS 0x80070000
|
||||
#define REGS_UARTDBG_SIZE 0x2000
|
||||
|
||||
#define HW_UARTDBGDR 0x00000000
|
||||
#define BP_UARTDBGDR_UNAVAILABLE 16
|
||||
#define BM_UARTDBGDR_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGDR_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGDR_UNAVAILABLE)
|
||||
#define BP_UARTDBGDR_RESERVED 12
|
||||
#define BM_UARTDBGDR_RESERVED 0x0000F000
|
||||
#define BF_UARTDBGDR_RESERVED(v) \
|
||||
(((v) << 12) & BM_UARTDBGDR_RESERVED)
|
||||
#define BM_UARTDBGDR_OE 0x00000800
|
||||
#define BM_UARTDBGDR_BE 0x00000400
|
||||
#define BM_UARTDBGDR_PE 0x00000200
|
||||
#define BM_UARTDBGDR_FE 0x00000100
|
||||
#define BP_UARTDBGDR_DATA 0
|
||||
#define BM_UARTDBGDR_DATA 0x000000FF
|
||||
#define BF_UARTDBGDR_DATA(v) \
|
||||
(((v) << 0) & BM_UARTDBGDR_DATA)
|
||||
#define HW_UARTDBGRSR_ECR 0x00000004
|
||||
#define BP_UARTDBGRSR_ECR_UNAVAILABLE 8
|
||||
#define BM_UARTDBGRSR_ECR_UNAVAILABLE 0xFFFFFF00
|
||||
#define BF_UARTDBGRSR_ECR_UNAVAILABLE(v) \
|
||||
(((v) << 8) & BM_UARTDBGRSR_ECR_UNAVAILABLE)
|
||||
#define BP_UARTDBGRSR_ECR_EC 4
|
||||
#define BM_UARTDBGRSR_ECR_EC 0x000000F0
|
||||
#define BF_UARTDBGRSR_ECR_EC(v) \
|
||||
(((v) << 4) & BM_UARTDBGRSR_ECR_EC)
|
||||
#define BM_UARTDBGRSR_ECR_OE 0x00000008
|
||||
#define BM_UARTDBGRSR_ECR_BE 0x00000004
|
||||
#define BM_UARTDBGRSR_ECR_PE 0x00000002
|
||||
#define BM_UARTDBGRSR_ECR_FE 0x00000001
|
||||
#define HW_UARTDBGFR 0x00000018
|
||||
#define BP_UARTDBGFR_UNAVAILABLE 16
|
||||
#define BM_UARTDBGFR_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGFR_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGFR_UNAVAILABLE)
|
||||
#define BP_UARTDBGFR_RESERVED 9
|
||||
#define BM_UARTDBGFR_RESERVED 0x0000FE00
|
||||
#define BF_UARTDBGFR_RESERVED(v) \
|
||||
(((v) << 9) & BM_UARTDBGFR_RESERVED)
|
||||
#define BM_UARTDBGFR_RI 0x00000100
|
||||
#define BM_UARTDBGFR_TXFE 0x00000080
|
||||
#define BM_UARTDBGFR_RXFF 0x00000040
|
||||
#define BM_UARTDBGFR_TXFF 0x00000020
|
||||
#define BM_UARTDBGFR_RXFE 0x00000010
|
||||
#define BM_UARTDBGFR_BUSY 0x00000008
|
||||
#define BM_UARTDBGFR_DCD 0x00000004
|
||||
#define BM_UARTDBGFR_DSR 0x00000002
|
||||
#define BM_UARTDBGFR_CTS 0x00000001
|
||||
#define HW_UARTDBGILPR 0x00000020
|
||||
#define BP_UARTDBGILPR_UNAVAILABLE 8
|
||||
#define BM_UARTDBGILPR_UNAVAILABLE 0xFFFFFF00
|
||||
#define BF_UARTDBGILPR_UNAVAILABLE(v) \
|
||||
(((v) << 8) & BM_UARTDBGILPR_UNAVAILABLE)
|
||||
#define BP_UARTDBGILPR_ILPDVSR 0
|
||||
#define BM_UARTDBGILPR_ILPDVSR 0x000000FF
|
||||
#define BF_UARTDBGILPR_ILPDVSR(v) \
|
||||
(((v) << 0) & BM_UARTDBGILPR_ILPDVSR)
|
||||
#define HW_UARTDBGIBRD 0x00000024
|
||||
#define BP_UARTDBGIBRD_UNAVAILABLE 16
|
||||
#define BM_UARTDBGIBRD_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGIBRD_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGIBRD_UNAVAILABLE)
|
||||
#define BP_UARTDBGIBRD_BAUD_DIVINT 0
|
||||
#define BM_UARTDBGIBRD_BAUD_DIVINT 0x0000FFFF
|
||||
#define BF_UARTDBGIBRD_BAUD_DIVINT(v) \
|
||||
(((v) << 0) & BM_UARTDBGIBRD_BAUD_DIVINT)
|
||||
#define HW_UARTDBGFBRD 0x00000028
|
||||
#define BP_UARTDBGFBRD_UNAVAILABLE 8
|
||||
#define BM_UARTDBGFBRD_UNAVAILABLE 0xFFFFFF00
|
||||
#define BF_UARTDBGFBRD_UNAVAILABLE(v) \
|
||||
(((v) << 8) & BM_UARTDBGFBRD_UNAVAILABLE)
|
||||
#define BP_UARTDBGFBRD_RESERVED 6
|
||||
#define BM_UARTDBGFBRD_RESERVED 0x000000C0
|
||||
#define BF_UARTDBGFBRD_RESERVED(v) \
|
||||
(((v) << 6) & BM_UARTDBGFBRD_RESERVED)
|
||||
#define BP_UARTDBGFBRD_BAUD_DIVFRAC 0
|
||||
#define BM_UARTDBGFBRD_BAUD_DIVFRAC 0x0000003F
|
||||
#define BF_UARTDBGFBRD_BAUD_DIVFRAC(v) \
|
||||
(((v) << 0) & BM_UARTDBGFBRD_BAUD_DIVFRAC)
|
||||
#define HW_UARTDBGLCR_H 0x0000002c
|
||||
#define BP_UARTDBGLCR_H_UNAVAILABLE 16
|
||||
#define BM_UARTDBGLCR_H_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGLCR_H_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGLCR_H_UNAVAILABLE)
|
||||
#define BP_UARTDBGLCR_H_RESERVED 8
|
||||
#define BM_UARTDBGLCR_H_RESERVED 0x0000FF00
|
||||
#define BF_UARTDBGLCR_H_RESERVED(v) \
|
||||
(((v) << 8) & BM_UARTDBGLCR_H_RESERVED)
|
||||
#define BM_UARTDBGLCR_H_SPS 0x00000080
|
||||
#define BP_UARTDBGLCR_H_WLEN 5
|
||||
#define BM_UARTDBGLCR_H_WLEN 0x00000060
|
||||
#define BF_UARTDBGLCR_H_WLEN(v) \
|
||||
(((v) << 5) & BM_UARTDBGLCR_H_WLEN)
|
||||
#define BM_UARTDBGLCR_H_FEN 0x00000010
|
||||
#define BM_UARTDBGLCR_H_STP2 0x00000008
|
||||
#define BM_UARTDBGLCR_H_EPS 0x00000004
|
||||
#define BM_UARTDBGLCR_H_PEN 0x00000002
|
||||
#define BM_UARTDBGLCR_H_BRK 0x00000001
|
||||
#define HW_UARTDBGCR 0x00000030
|
||||
#define BP_UARTDBGCR_UNAVAILABLE 16
|
||||
#define BM_UARTDBGCR_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGCR_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGCR_UNAVAILABLE)
|
||||
#define BM_UARTDBGCR_CTSEN 0x00008000
|
||||
#define BM_UARTDBGCR_RTSEN 0x00004000
|
||||
#define BM_UARTDBGCR_OUT2 0x00002000
|
||||
#define BM_UARTDBGCR_OUT1 0x00001000
|
||||
#define BM_UARTDBGCR_RTS 0x00000800
|
||||
#define BM_UARTDBGCR_DTR 0x00000400
|
||||
#define BM_UARTDBGCR_RXE 0x00000200
|
||||
#define BM_UARTDBGCR_TXE 0x00000100
|
||||
#define BM_UARTDBGCR_LBE 0x00000080
|
||||
#define BP_UARTDBGCR_RESERVED 3
|
||||
#define BM_UARTDBGCR_RESERVED 0x00000078
|
||||
#define BF_UARTDBGCR_RESERVED(v) \
|
||||
(((v) << 3) & BM_UARTDBGCR_RESERVED)
|
||||
#define BM_UARTDBGCR_SIRLP 0x00000004
|
||||
#define BM_UARTDBGCR_SIREN 0x00000002
|
||||
#define BM_UARTDBGCR_UARTEN 0x00000001
|
||||
#define HW_UARTDBGIFLS 0x00000034
|
||||
#define BP_UARTDBGIFLS_UNAVAILABLE 16
|
||||
#define BM_UARTDBGIFLS_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGIFLS_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGIFLS_UNAVAILABLE)
|
||||
#define BP_UARTDBGIFLS_RESERVED 6
|
||||
#define BM_UARTDBGIFLS_RESERVED 0x0000FFC0
|
||||
#define BF_UARTDBGIFLS_RESERVED(v) \
|
||||
(((v) << 6) & BM_UARTDBGIFLS_RESERVED)
|
||||
#define BP_UARTDBGIFLS_RXIFLSEL 3
|
||||
#define BM_UARTDBGIFLS_RXIFLSEL 0x00000038
|
||||
#define BF_UARTDBGIFLS_RXIFLSEL(v) \
|
||||
(((v) << 3) & BM_UARTDBGIFLS_RXIFLSEL)
|
||||
#define BV_UARTDBGIFLS_RXIFLSEL__NOT_EMPTY 0x0
|
||||
#define BV_UARTDBGIFLS_RXIFLSEL__ONE_QUARTER 0x1
|
||||
#define BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF 0x2
|
||||
#define BV_UARTDBGIFLS_RXIFLSEL__THREE_QUARTERS 0x3
|
||||
#define BV_UARTDBGIFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4
|
||||
#define BV_UARTDBGIFLS_RXIFLSEL__INVALID5 0x5
|
||||
#define BV_UARTDBGIFLS_RXIFLSEL__INVALID6 0x6
|
||||
#define BV_UARTDBGIFLS_RXIFLSEL__INVALID7 0x7
|
||||
#define BP_UARTDBGIFLS_TXIFLSEL 0
|
||||
#define BM_UARTDBGIFLS_TXIFLSEL 0x00000007
|
||||
#define BF_UARTDBGIFLS_TXIFLSEL(v) \
|
||||
(((v) << 0) & BM_UARTDBGIFLS_TXIFLSEL)
|
||||
#define BV_UARTDBGIFLS_TXIFLSEL__EMPTY 0x0
|
||||
#define BV_UARTDBGIFLS_TXIFLSEL__ONE_QUARTER 0x1
|
||||
#define BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF 0x2
|
||||
#define BV_UARTDBGIFLS_TXIFLSEL__THREE_QUARTERS 0x3
|
||||
#define BV_UARTDBGIFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4
|
||||
#define BV_UARTDBGIFLS_TXIFLSEL__INVALID5 0x5
|
||||
#define BV_UARTDBGIFLS_TXIFLSEL__INVALID6 0x6
|
||||
#define BV_UARTDBGIFLS_TXIFLSEL__INVALID7 0x7
|
||||
#define HW_UARTDBGIMSC 0x00000038
|
||||
#define BP_UARTDBGIMSC_UNAVAILABLE 16
|
||||
#define BM_UARTDBGIMSC_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGIMSC_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGIMSC_UNAVAILABLE)
|
||||
#define BP_UARTDBGIMSC_RESERVED 11
|
||||
#define BM_UARTDBGIMSC_RESERVED 0x0000F800
|
||||
#define BF_UARTDBGIMSC_RESERVED(v) \
|
||||
(((v) << 11) & BM_UARTDBGIMSC_RESERVED)
|
||||
#define BM_UARTDBGIMSC_OEIM 0x00000400
|
||||
#define BM_UARTDBGIMSC_BEIM 0x00000200
|
||||
#define BM_UARTDBGIMSC_PEIM 0x00000100
|
||||
#define BM_UARTDBGIMSC_FEIM 0x00000080
|
||||
#define BM_UARTDBGIMSC_RTIM 0x00000040
|
||||
#define BM_UARTDBGIMSC_TXIM 0x00000020
|
||||
#define BM_UARTDBGIMSC_RXIM 0x00000010
|
||||
#define BM_UARTDBGIMSC_DSRMIM 0x00000008
|
||||
#define BM_UARTDBGIMSC_DCDMIM 0x00000004
|
||||
#define BM_UARTDBGIMSC_CTSMIM 0x00000002
|
||||
#define BM_UARTDBGIMSC_RIMIM 0x00000001
|
||||
#define HW_UARTDBGRIS 0x0000003c
|
||||
#define BP_UARTDBGRIS_UNAVAILABLE 16
|
||||
#define BM_UARTDBGRIS_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGRIS_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGRIS_UNAVAILABLE)
|
||||
#define BP_UARTDBGRIS_RESERVED 11
|
||||
#define BM_UARTDBGRIS_RESERVED 0x0000F800
|
||||
#define BF_UARTDBGRIS_RESERVED(v) \
|
||||
(((v) << 11) & BM_UARTDBGRIS_RESERVED)
|
||||
#define BM_UARTDBGRIS_OERIS 0x00000400
|
||||
#define BM_UARTDBGRIS_BERIS 0x00000200
|
||||
#define BM_UARTDBGRIS_PERIS 0x00000100
|
||||
#define BM_UARTDBGRIS_FERIS 0x00000080
|
||||
#define BM_UARTDBGRIS_RTRIS 0x00000040
|
||||
#define BM_UARTDBGRIS_TXRIS 0x00000020
|
||||
#define BM_UARTDBGRIS_RXRIS 0x00000010
|
||||
#define BM_UARTDBGRIS_DSRRMIS 0x00000008
|
||||
#define BM_UARTDBGRIS_DCDRMIS 0x00000004
|
||||
#define BM_UARTDBGRIS_CTSRMIS 0x00000002
|
||||
#define BM_UARTDBGRIS_RIRMIS 0x00000001
|
||||
#define HW_UARTDBGMIS 0x00000040
|
||||
#define BP_UARTDBGMIS_UNAVAILABLE 16
|
||||
#define BM_UARTDBGMIS_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGMIS_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGMIS_UNAVAILABLE)
|
||||
#define BP_UARTDBGMIS_RESERVED 11
|
||||
#define BM_UARTDBGMIS_RESERVED 0x0000F800
|
||||
#define BF_UARTDBGMIS_RESERVED(v) \
|
||||
(((v) << 11) & BM_UARTDBGMIS_RESERVED)
|
||||
#define BM_UARTDBGMIS_OEMIS 0x00000400
|
||||
#define BM_UARTDBGMIS_BEMIS 0x00000200
|
||||
#define BM_UARTDBGMIS_PEMIS 0x00000100
|
||||
#define BM_UARTDBGMIS_FEMIS 0x00000080
|
||||
#define BM_UARTDBGMIS_RTMIS 0x00000040
|
||||
#define BM_UARTDBGMIS_TXMIS 0x00000020
|
||||
#define BM_UARTDBGMIS_RXMIS 0x00000010
|
||||
#define BM_UARTDBGMIS_DSRMMIS 0x00000008
|
||||
#define BM_UARTDBGMIS_DCDMMIS 0x00000004
|
||||
#define BM_UARTDBGMIS_CTSMMIS 0x00000002
|
||||
#define BM_UARTDBGMIS_RIMMIS 0x00000001
|
||||
#define HW_UARTDBGICR 0x00000044
|
||||
#define BP_UARTDBGICR_UNAVAILABLE 16
|
||||
#define BM_UARTDBGICR_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGICR_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGICR_UNAVAILABLE)
|
||||
#define BP_UARTDBGICR_RESERVED 11
|
||||
#define BM_UARTDBGICR_RESERVED 0x0000F800
|
||||
#define BF_UARTDBGICR_RESERVED(v) \
|
||||
(((v) << 11) & BM_UARTDBGICR_RESERVED)
|
||||
#define BM_UARTDBGICR_OEIC 0x00000400
|
||||
#define BM_UARTDBGICR_BEIC 0x00000200
|
||||
#define BM_UARTDBGICR_PEIC 0x00000100
|
||||
#define BM_UARTDBGICR_FEIC 0x00000080
|
||||
#define BM_UARTDBGICR_RTIC 0x00000040
|
||||
#define BM_UARTDBGICR_TXIC 0x00000020
|
||||
#define BM_UARTDBGICR_RXIC 0x00000010
|
||||
#define BM_UARTDBGICR_DSRMIC 0x00000008
|
||||
#define BM_UARTDBGICR_DCDMIC 0x00000004
|
||||
#define BM_UARTDBGICR_CTSMIC 0x00000002
|
||||
#define BM_UARTDBGICR_RIMIC 0x00000001
|
||||
#define HW_UARTDBGDMACR 0x00000048
|
||||
#define BP_UARTDBGDMACR_UNAVAILABLE 16
|
||||
#define BM_UARTDBGDMACR_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGDMACR_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGDMACR_UNAVAILABLE)
|
||||
#define BP_UARTDBGDMACR_RESERVED 3
|
||||
#define BM_UARTDBGDMACR_RESERVED 0x0000FFF8
|
||||
#define BF_UARTDBGDMACR_RESERVED(v) \
|
||||
(((v) << 3) & BM_UARTDBGDMACR_RESERVED)
|
||||
#define BM_UARTDBGDMACR_DMAONERR 0x00000004
|
||||
#define BM_UARTDBGDMACR_TXDMAE 0x00000002
|
||||
#define BM_UARTDBGDMACR_RXDMAE 0x00000001
|
||||
22
arch/arm/mach-stmp37xx/include/mach/regs-usbctl.h
Normal file
22
arch/arm/mach-stmp37xx/include/mach/regs-usbctl.h
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* stmp37xx: USBCTL register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_USBCTL_BASE (STMP3XXX_REGS_BASE + 0x80000)
|
||||
#define REGS_USBCTL_PHYS 0x80000
|
||||
22
arch/arm/mach-stmp37xx/include/mach/regs-usbctrl.h
Normal file
22
arch/arm/mach-stmp37xx/include/mach/regs-usbctrl.h
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* stmp37xx: USBCTRL register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_USBCTRL_BASE (STMP3XXX_REGS_BASE + 0x80000)
|
||||
#define REGS_USBCTRL_PHYS 0x80080000
|
||||
37
arch/arm/mach-stmp37xx/include/mach/regs-usbphy.h
Normal file
37
arch/arm/mach-stmp37xx/include/mach/regs-usbphy.h
Normal file
|
|
@ -0,0 +1,37 @@
|
|||
/*
|
||||
* stmp37xx: USBPHY register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_USBPHY_BASE (STMP3XXX_REGS_BASE + 0x7C000)
|
||||
|
||||
#define HW_USBPHY_PWD 0x0
|
||||
|
||||
#define HW_USBPHY_CTRL 0x30
|
||||
#define BM_USBPHY_CTRL_ENHSPRECHARGEXMIT 0x00000001
|
||||
#define BP_USBPHY_CTRL_ENHSPRECHARGEXMIT 0
|
||||
#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT 0x00000002
|
||||
#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT 0x00000010
|
||||
#define BM_USBPHY_CTRL_ENOTGIDDETECT 0x00000080
|
||||
#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN 0x00000800
|
||||
#define BM_USBPHY_CTRL_CLKGATE 0x40000000
|
||||
#define BM_USBPHY_CTRL_SFTRST 0x80000000
|
||||
|
||||
#define HW_USBPHY_STATUS 0x40
|
||||
#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS 0x00000040
|
||||
#define BM_USBPHY_STATUS_OTGID_STATUS 0x00000100
|
||||
Loading…
Reference in a new issue