adulau/aha
1
0
Fork 0
mirror of https://github.com/adulau/aha.git synced 2025-01-03 14:43:17 +00:00
Code Issues Projects Releases Packages Wiki Activity

Merge branch 'omap-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6

Browse source
This commit is contained in:
Russell King 2009-06-25 13:47:21 +01:00 committed by Russell King
commit f9bfccf11d
14 changed files with 108 additions and 22 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
arch/arm/mach-omap1/board-nokia770.c
View file

@ -36,7 +36,6 @@
#include <mach/hwa742.h>
#include <mach/lcd_mipid.h>
#include <mach/mmc.h>
#include <mach/usb.h>
#include <mach/clock.h>
#define ADS7846_PENDOWN_GPIO 15
@ -205,9 +204,11 @@ static int nokia770_mmc_get_cover_state(struct device *dev, int slot)
static struct omap_mmc_platform_data nokia770_mmc2_data = {
.nr_slots = 1,
.dma_mask = 0xffffffff,
.max_freq = 12000000,
.slots[0] = {
.set_power = nokia770_mmc_set_power,
.get_cover_state = nokia770_mmc_get_cover_state,
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
.name = "mmcblk",
},
};

2
arch/arm/mach-omap1/mailbox.c
View file

@ -203,5 +203,5 @@ module_exit(omap1_mbox_exit);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("omap mailbox: omap1 architecture specific functions");
MODULE_AUTHOR("Hiroshi DOYU" <Hiroshi.DOYU@nokia.com>);
MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
MODULE_ALIAS("platform:omap1-mailbox");

1
arch/arm/mach-omap2/board-rx51-peripherals.c
View file

@ -362,6 +362,7 @@ static struct omap_onenand_platform_data board_onenand_data = {
.gpio_irq = 65,
.parts = onenand_partitions,
.nr_parts = ARRAY_SIZE(onenand_partitions),
.flags = ONENAND_SYNC_READWRITE,
};
static void __init board_onenand_init(void)

21
arch/arm/mach-omap2/gpmc-onenand.c
View file

@ -31,6 +31,8 @@ static struct platform_device gpmc_onenand_device = {
static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
{
struct gpmc_timings t;
u32 reg;
int err;
const int t_cer = 15;
const int t_avdp = 12;
@ -43,6 +45,11 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
const int t_wpl = 40;
const int t_wph = 30;
/* Ensure sync read and sync write are disabled */
reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
memset(&t, 0, sizeof(t));
t.sync_clk = 0;
t.cs_on = 0;
@ -74,7 +81,16 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
GPMC_CONFIG1_DEVICESIZE_16 |
GPMC_CONFIG1_MUXADDDATA);
return gpmc_cs_set_timings(cs, &t);
err = gpmc_cs_set_timings(cs, &t);
if (err)
return err;
/* Ensure sync read and sync write are disabled */
reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
return 0;
}
static void set_onenand_cfg(void __iomem *onenand_base, int latency,
@ -124,7 +140,8 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
} else if (cfg->flags & ONENAND_SYNC_READWRITE) {
sync_read = 1;
sync_write = 1;
}
} else
return omap2_onenand_set_async_mode(cs, onenand_base);
if (!freq) {
/* Very first call freq is not known */

22
arch/arm/mach-omap2/id.c
View file

@ -48,6 +48,28 @@ int omap_chip_is(struct omap_chip_id oci)
}
EXPORT_SYMBOL(omap_chip_is);
int omap_type(void)
{
u32 val = 0;
if (cpu_is_omap24xx())
val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
else if (cpu_is_omap34xx())
val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
else {
pr_err("Cannot detect omap type!\n");
goto out;
}
val &= OMAP2_DEVICETYPE_MASK;
val >>= 8;
out:
return val;
}
EXPORT_SYMBOL(omap_type);
/*----------------------------------------------------------------------------*/
#define OMAP_TAP_IDCODE 0x0204

6
arch/arm/mach-omap2/mailbox.c
View file

@ -282,12 +282,12 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev)
return -ENOMEM;
/* DSP or IVA2 IRQ */
mbox_dsp_info.irq = platform_get_irq(pdev, 0);
if (mbox_dsp_info.irq < 0) {
ret = platform_get_irq(pdev, 0);
if (ret < 0) {
dev_err(&pdev->dev, "invalid irq resource\n");
ret = -ENODEV;
goto err_dsp;
}
mbox_dsp_info.irq = ret;
ret = omap_mbox_register(&pdev->dev, &mbox_dsp_info);
if (ret)

13
arch/arm/mach-omap2/mmc-twl4030.c
View file

@ -263,8 +263,19 @@ static int twl_mmc1_set_power(struct device *dev, int slot, int power_on,
static int twl_mmc23_set_power(struct device *dev, int slot, int power_on, int vdd)
{
int ret = 0;
struct twl_mmc_controller *c = &hsmmc[1];
struct twl_mmc_controller *c = NULL;
struct omap_mmc_platform_data *mmc = dev->platform_data;
int i;
for (i = 1; i < ARRAY_SIZE(hsmmc); i++) {
if (mmc == hsmmc[i].mmc) {
c = &hsmmc[i];
break;
}
}
if (c == NULL)
return -ENODEV;
/* If we don't see a Vcc regulator, assume it's a fixed
* voltage always-on regulator.

13
arch/arm/plat-omap/dma.c
View file

@ -2457,6 +2457,19 @@ static int __init omap_init_dma(void)
setup_irq(irq, &omap24xx_dma_irq);
}
/* Enable smartidle idlemodes and autoidle */
if (cpu_is_omap34xx()) {
u32 v = dma_read(OCP_SYSCONFIG);
v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
DMA_SYSCONFIG_SIDLEMODE_MASK |
DMA_SYSCONFIG_AUTOIDLE);
v |= (DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
DMA_SYSCONFIG_AUTOIDLE);
dma_write(v , OCP_SYSCONFIG);
}
/* FIXME: Update LCD DMA to work on 24xx */
if (cpu_class_is_omap1()) {
r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,

1
arch/arm/plat-omap/gpio.c
View file

@ -1585,6 +1585,7 @@ static int __init _omap_gpio_init(void)
__raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
__raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
__raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
__raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_DEBOUNCE_EN);
/* Initialize interface clock ungated, module enabled */
__raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);

22
arch/arm/plat-omap/include/mach/cpu.h
View file

@ -30,6 +30,17 @@
#ifndef __ASM_ARCH_OMAP_CPU_H
#define __ASM_ARCH_OMAP_CPU_H
/*
* Omap device type i.e. EMU/HS/TST/GP/BAD
*/
#define OMAP2_DEVICE_TYPE_TEST 0
#define OMAP2_DEVICE_TYPE_EMU 1
#define OMAP2_DEVICE_TYPE_SEC 2
#define OMAP2_DEVICE_TYPE_GP 3
#define OMAP2_DEVICE_TYPE_BAD 4
int omap_type(void);
struct omap_chip_id {
u8 oc;
u8 type;
@ -424,17 +435,6 @@ IS_OMAP_TYPE(3430, 0x3430)
int omap_chip_is(struct omap_chip_id oci);
int omap_type(void);
/*
* Macro to detect device type i.e. EMU/HS/TST/GP/BAD
*/
#define OMAP2_DEVICE_TYPE_TEST 0
#define OMAP2_DEVICE_TYPE_EMU 1
#define OMAP2_DEVICE_TYPE_SEC 2
#define OMAP2_DEVICE_TYPE_GP 3
#define OMAP2_DEVICE_TYPE_BAD 4
void omap2_check_revision(void);
#endif /* defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) */

15
arch/arm/plat-omap/include/mach/dma.h
View file

@ -389,6 +389,21 @@
#define DMA_THREAD_FIFO_25 (0x02 << 14)
#define DMA_THREAD_FIFO_50 (0x03 << 14)
/* DMA4_OCP_SYSCONFIG bits */
#define DMA_SYSCONFIG_MIDLEMODE_MASK (3 << 12)
#define DMA_SYSCONFIG_CLOCKACTIVITY_MASK (3 << 8)
#define DMA_SYSCONFIG_EMUFREE (1 << 5)
#define DMA_SYSCONFIG_SIDLEMODE_MASK (3 << 3)
#define DMA_SYSCONFIG_SOFTRESET (1 << 2)
#define DMA_SYSCONFIG_AUTOIDLE (1 << 0)
#define DMA_SYSCONFIG_MIDLEMODE(n) ((n) << 12)
#define DMA_SYSCONFIG_SIDLEMODE(n) ((n) << 3)
#define DMA_IDLEMODE_SMARTIDLE 0x2
#define DMA_IDLEMODE_NO_IDLE 0x1
#define DMA_IDLEMODE_FORCE_IDLE 0x0
/* Chaining modes*/
#ifndef CONFIG_ARCH_OMAP1
#define OMAP_DMA_STATIC_CHAIN 0x1

2
arch/arm/plat-omap/include/mach/io.h
View file

@ -201,7 +201,7 @@
#define OMAP2_IO_ADDRESS(pa) IOMEM(__OMAP2_IO_ADDRESS(pa))
#ifdef __ASSEMBLER__
#define IOMEM(x) x
#define IOMEM(x) (x)
#else
#define IOMEM(x) ((void __force __iomem *)(x))

2
arch/arm/plat-omap/iommu.c
View file

@ -298,7 +298,7 @@ void flush_iotlb_page(struct iommu *obj, u32 da)
if ((start <= da) && (da < start + bytes)) {
dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n",
__func__, start, da, bytes);
iotlb_load_cr(obj, &cr);
iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
}
}

7
arch/arm/plat-omap/sram.c
View file

@ -133,7 +133,12 @@ void __init omap_detect_sram(void)
if (cpu_is_omap34xx()) {
omap_sram_base = OMAP3_SRAM_PUB_VA;
omap_sram_start = OMAP3_SRAM_PUB_PA;
omap_sram_size = 0x8000; /* 32K */
if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
(omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
omap_sram_size = 0x7000; /* 28K */
} else {
omap_sram_size = 0x8000; /* 32K */
}
} else {
omap_sram_base = OMAP2_SRAM_PUB_VA;
omap_sram_start = OMAP2_SRAM_PUB_PA;