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MIPS: For Cavium OCTEON set hwrena and lazily restore CP2 state.
If on Cavium, be aware of cop2 and hwrena during do_cpu(). Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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1 changed files with 21 additions and 0 deletions
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@ -47,6 +47,7 @@
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#include <asm/mmu_context.h>
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#include <asm/mmu_context.h>
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#include <asm/types.h>
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#include <asm/types.h>
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#include <asm/stacktrace.h>
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#include <asm/stacktrace.h>
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#include <asm/irq.h>
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extern void check_wait(void);
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extern void check_wait(void);
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extern asmlinkage void r4k_wait(void);
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extern asmlinkage void r4k_wait(void);
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@ -78,6 +79,10 @@ extern asmlinkage void handle_reserved(void);
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extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
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extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
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struct mips_fpu_struct *ctx, int has_fpu);
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struct mips_fpu_struct *ctx, int has_fpu);
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task);
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#endif
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void (*board_be_init)(void);
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void (*board_be_init)(void);
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int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
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int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
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void (*board_nmi_handler_setup)(void);
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void (*board_nmi_handler_setup)(void);
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@ -860,6 +865,7 @@ asmlinkage void do_cpu(struct pt_regs *regs)
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unsigned int opcode;
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unsigned int opcode;
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unsigned int cpid;
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unsigned int cpid;
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int status;
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int status;
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unsigned long __maybe_unused flags;
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die_if_kernel("do_cpu invoked from kernel context!", regs);
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die_if_kernel("do_cpu invoked from kernel context!", regs);
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@ -915,6 +921,17 @@ asmlinkage void do_cpu(struct pt_regs *regs)
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return;
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return;
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case 2:
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case 2:
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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prefetch(¤t->thread.cp2);
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local_irq_save(flags);
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KSTK_STATUS(current) |= ST0_CU2;
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status = read_c0_status();
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write_c0_status(status | ST0_CU2);
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octeon_cop2_restore(&(current->thread.cp2));
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write_c0_status(status & ~ST0_CU2);
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local_irq_restore(flags);
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return;
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#endif
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case 3:
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case 3:
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break;
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break;
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}
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}
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@ -1488,6 +1505,10 @@ void __cpuinit per_cpu_trap_init(void)
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write_c0_hwrena(enable);
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write_c0_hwrena(enable);
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}
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}
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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write_c0_hwrena(0xc000000f); /* Octeon has register 30 and 31 */
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#endif
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#ifdef CONFIG_MIPS_MT_SMTC
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#ifdef CONFIG_MIPS_MT_SMTC
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if (!secondaryTC) {
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if (!secondaryTC) {
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#endif /* CONFIG_MIPS_MT_SMTC */
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#endif /* CONFIG_MIPS_MT_SMTC */
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