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[PATCH] gxfb: Fixups for the AMD Geode GX framebuffer driver
We cannot assume that the BIOS will be correctly setting up the hardware, so set some bits in various display registers to enable video output. Allow an advanced user to specify a frambuffer size, rather then probing the BIOS. All of these fixes were prompted by the OLPC effort. [akpm@osdl.org: cleanups] Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Cc: "Antonino A. Daplas" <adaplas@pol.net> Acked-by: James Simmons <jsimmons@infradead.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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4c1979c896
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6 changed files with 65 additions and 1 deletions
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@ -23,6 +23,26 @@ config FB_GEODE_GX
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If unsure, say N.
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config FB_GEODE_GX_SET_FBSIZE
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bool "Manually specify the Geode GX framebuffer size"
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depends on FB_GEODE_GX
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default n
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---help---
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If you want to manually specify the size of your GX framebuffer,
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say Y here, otherwise say N to dynamically probe it.
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Say N unless you know what you are doing.
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config FB_GEODE_GX_FBSIZE
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hex "Size of the GX framebuffer, in bytes"
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depends on FB_GEODE_GX_SET_FBSIZE
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default "0x1600000"
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---help---
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Specify the size of the GX framebuffer. Normally, you will
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want this to be MB aligned. Common values are 0x80000 (8MB)
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and 0x1600000 (16MB). Don't change this unless you know what
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you are doing
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config FB_GEODE_GX1
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tristate "AMD Geode GX1 framebuffer support (EXPERIMENTAL)"
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depends on FB && FB_GEODE && EXPERIMENTAL
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@ -21,6 +21,12 @@
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#include "geodefb.h"
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#include "display_gx.h"
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#ifdef CONFIG_FB_GEODE_GX_SET_FBSIZE
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unsigned int gx_frame_buffer_size(void)
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{
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return CONFIG_FB_GEODE_GX_FBSIZE;
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}
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#else
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unsigned int gx_frame_buffer_size(void)
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{
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unsigned int val;
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@ -35,6 +41,7 @@ unsigned int gx_frame_buffer_size(void)
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val = (unsigned int)(inw(0xAC1E)) & 0xFFl;
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return (val << 19);
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}
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#endif
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int gx_line_delta(int xres, int bpp)
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{
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@ -90,6 +97,7 @@ static void gx_set_mode(struct fb_info *info)
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writel(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2,
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par->dc_regs + DC_LINE_SIZE);
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/* Enable graphics and video data and unmask address lines. */
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dcfg |= DC_DCFG_GDEN | DC_DCFG_VDEN | DC_DCFG_A20M | DC_DCFG_A18M;
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@ -93,4 +93,5 @@ extern struct geode_dc_ops gx_dc_ops;
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#define DC_PAL_ADDRESS 0x70
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#define DC_PAL_DATA 0x74
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#define DC_GLIU0_MEM_OFFSET 0x84
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#endif /* !__DISPLAY_GX1_H__ */
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@ -240,6 +240,12 @@ static int __init gxfb_map_video_memory(struct fb_info *info, struct pci_dev *de
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if (!info->screen_base)
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return -ENOMEM;
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/* Set the 16MB aligned base address of the graphics memory region
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* in the display controller */
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writel(info->fix.smem_start & 0xFF000000,
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par->dc_regs + DC_GLIU0_MEM_OFFSET);
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dev_info(&dev->dev, "%d Kibyte of video memory at 0x%lx\n",
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info->fix.smem_len / 1024, info->fix.smem_start);
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@ -178,7 +178,21 @@ static void gx_set_dclk_frequency(struct fb_info *info)
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static void gx_configure_display(struct fb_info *info)
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{
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struct geodefb_par *par = info->par;
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u32 dcfg, fp_pm;
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u32 dcfg, fp_pm, misc;
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/* Set up the MISC register */
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misc = readl(par->vid_regs + GX_MISC);
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/* Power up the DAC */
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misc &= ~(GX_MISC_A_PWRDN | GX_MISC_DAC_PWRDN);
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/* Disable gamma correction */
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misc |= GX_MISC_GAM_EN;
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writel(misc, par->vid_regs + GX_MISC);
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/* Write the display configuration */
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dcfg = readl(par->vid_regs + GX_DCFG);
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@ -199,9 +213,17 @@ static void gx_configure_display(struct fb_info *info)
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if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
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dcfg |= GX_DCFG_CRT_VSYNC_POL;
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/* Enable the display logic */
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/* Set up the DACS to blank normally */
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dcfg |= GX_DCFG_CRT_EN | GX_DCFG_DAC_BL_EN;
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/* Enable the external DAC VREF? */
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writel(dcfg, par->vid_regs + GX_DCFG);
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/* Power on flat panel. */
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fp_pm = readl(par->vid_regs + GX_FP_PM);
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fp_pm |= GX_FP_PM_P;
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writel(fp_pm, par->vid_regs + GX_FP_PM);
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@ -28,6 +28,13 @@ extern struct geode_vid_ops gx_vid_ops;
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# define GX_DCFG_GV_GAM 0x00200000
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# define GX_DCFG_DAC_VREF 0x04000000
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/* Geode GX MISC video configuration */
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#define GX_MISC 0x50
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#define GX_MISC_GAM_EN 0x00000001
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#define GX_MISC_DAC_PWRDN 0x00000400
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#define GX_MISC_A_PWRDN 0x00000800
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/* Geode GX flat panel display control registers */
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#define GX_FP_PM 0x410
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# define GX_FP_PM_P 0x01000000
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