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m68knommu: remove interrupt masking from ColdFire pit timer

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With proper interrupt controller code in place there is no need for
devices like the timers to have custom interrupt masking code.
Remove it (and the defines that go along with it).

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
This commit is contained in:
Greg Ungerer 2009-05-06 11:36:00 +10:00
parent a3d9bf1dfd
commit f1a59d244a
3 changed files with 0 additions and 26 deletions
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4
arch/m68k/include/asm/m520xsim.h
View file

@ -124,10 +124,6 @@
#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02)
#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04)
#define ICR_INTRCONF 0x05
#define MCFPIT_IMR MCFINTC_IMRL
#define MCFPIT_IMR_IBIT (1 << MCFINT_PIT1)
/*
* Reset Controll Unit.
*/

14
arch/m68k/include/asm/mcfsim.h
View file

@ -101,20 +101,6 @@
#endif
/*
* PIT interrupt settings, if not found in mXXXXsim.h file.
*/
#ifndef ICR_INTRCONF
#define ICR_INTRCONF 0x2b /* PIT1 level 5, priority 3 */
#endif
#ifndef MCFPIT_IMR
#define MCFPIT_IMR MCFINTC_IMRH
#endif
#ifndef MCFPIT_IMR_IBIT
#define MCFPIT_IMR_IBIT (1 << (MCFINT_PIT1 - 32))
#endif
#ifndef __ASSEMBLY__
/*
* Definition for the interrupt auto-vectoring support.

8
arch/m68knommu/platform/coldfire/pit.c
View file

@ -32,7 +32,6 @@
*/
#define FREQ ((MCF_CLK / 2) / 64)
#define TA(a) (MCF_IPSBAR + MCFPIT_BASE1 + (a))
#define INTC0 (MCF_IPSBAR + MCFICM_INTC0)
#define PIT_CYCLES_PER_JIFFY (FREQ / HZ)
static u32 pit_cnt;
@ -154,8 +153,6 @@ static struct clocksource pit_clk = {
void hw_timer_init(void)
{
u32 imr;
cf_pit_clockevent.cpumask = cpumask_of(smp_processor_id());
cf_pit_clockevent.mult = div_sc(FREQ, NSEC_PER_SEC, 32);
cf_pit_clockevent.max_delta_ns =
@ -166,11 +163,6 @@ void hw_timer_init(void)
setup_irq(MCFINT_VECBASE + MCFINT_PIT1, &pit_irq);
__raw_writeb(ICR_INTRCONF, INTC0 + MCFINTC_ICR0 + MCFINT_PIT1);
imr = __raw_readl(INTC0 + MCFPIT_IMR);
imr &= ~MCFPIT_IMR_IBIT;
__raw_writel(imr, INTC0 + MCFPIT_IMR);
pit_clk.mult = clocksource_hz2mult(FREQ, pit_clk.shift);
clocksource_register(&pit_clk);
}