mirror of
https://github.com/adulau/aha.git
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Merge branch 'sh/for-2.6.33' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6
* 'sh/for-2.6.33' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: sh: Ensure all PG_dcache_dirty pages are written back. sh: mach-ecovec24: setup.c detailed correction serial: sh-sci: Convert tremaining ctrl_xxx I/O routines to __raw_xxx. serial: sh-sci: earlyprintk zero uartclk fix sh: Only use bl bit toggling for sleeping idle. sh: Restore bl bit toggling in idle loop. sh: Fix up MAX_DMA_CHANNELS definition when DMA is disabled. sh: dmaengine support for SH7785 sh: dmaengine support for sh7724.
This commit is contained in:
Linus Torvalds
commit
ef2c55e5c6
9 changed files with 117 additions and 78 deletions
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@ -128,8 +128,6 @@ static struct platform_device nor_flash_device = {
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/* SH Eth */
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#define SH_ETH_ADDR (0xA4600000)
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#define SH_ETH_MAHR (SH_ETH_ADDR + 0x1C0)
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#define SH_ETH_MALR (SH_ETH_ADDR + 0x1C8)
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static struct resource sh_eth_resources[] = {
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[0] = {
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.start = SH_ETH_ADDR,
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@ -509,6 +507,7 @@ static struct platform_device sdhi1_device = {
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#else
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/* MMC SPI */
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static int mmc_spi_get_ro(struct device *dev)
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{
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return gpio_get_value(GPIO_PTY6);
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@ -542,6 +541,7 @@ static struct spi_board_info spi_bus[] = {
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},
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};
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/* MSIOF0 */
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static struct sh_msiof_spi_info msiof0_data = {
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.num_chipselect = 1,
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};
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@ -19,9 +19,11 @@
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#include <asm-generic/dma.h>
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#ifdef CONFIG_NR_DMA_CHANNELS
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# define MAX_DMA_CHANNELS (CONFIG_NR_DMA_CHANNELS)
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# define MAX_DMA_CHANNELS (CONFIG_NR_DMA_CHANNELS)
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#elif defined(CONFIG_NR_ONCHIP_DMA_CHANNELS)
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# define MAX_DMA_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS)
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#else
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# define MAX_DMA_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS)
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# define MAX_DMA_CHANNELS 0
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#endif
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/*
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@ -19,10 +19,10 @@
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#elif defined(CONFIG_CPU_SUBTYPE_SH7723) || \
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defined(CONFIG_CPU_SUBTYPE_SH7724)
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#define DMTE0_IRQ 48 /* DMAC0A*/
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#define DMTE4_IRQ 40 /* DMAC0B */
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#define DMTE6_IRQ 42
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#define DMTE8_IRQ 76 /* DMAC1A */
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#define DMTE9_IRQ 77
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#define DMTE4_IRQ 76 /* DMAC0B */
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#define DMTE6_IRQ 40
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#define DMTE8_IRQ 42 /* DMAC1A */
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#define DMTE9_IRQ 43
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#define DMTE10_IRQ 72 /* DMAC1B */
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#define DMTE11_IRQ 73
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#define DMAE0_IRQ 78 /* DMA Error IRQ*/
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@ -23,9 +23,23 @@
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#include <linux/notifier.h>
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#include <asm/suspend.h>
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#include <asm/clock.h>
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#include <asm/dma-sh.h>
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#include <asm/mmzone.h>
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#include <cpu/sh7724.h>
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/* DMA */
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static struct sh_dmae_pdata dma_platform_data = {
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.mode = SHDMA_DMAOR1,
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};
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static struct platform_device dma_device = {
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.name = "sh-dma-engine",
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.id = -1,
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.dev = {
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.platform_data = &dma_platform_data,
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},
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};
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/* Serial */
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static struct plat_sci_port scif0_platform_data = {
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.mapbase = 0xffe00000,
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@ -649,6 +663,7 @@ static struct platform_device *sh7724_devices[] __initdata = {
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&tmu3_device,
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&tmu4_device,
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&tmu5_device,
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&dma_device,
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&rtc_device,
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&iic0_device,
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&iic1_device,
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@ -14,6 +14,7 @@
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#include <linux/io.h>
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#include <linux/mm.h>
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#include <linux/sh_timer.h>
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#include <asm/dma-sh.h>
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#include <asm/mmzone.h>
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static struct plat_sci_port scif0_platform_data = {
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@ -294,6 +295,18 @@ static struct platform_device tmu5_device = {
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.num_resources = ARRAY_SIZE(tmu5_resources),
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};
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static struct sh_dmae_pdata dma_platform_data = {
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.mode = (SHDMA_MIX_IRQ | SHDMA_DMAOR1),
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};
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static struct platform_device dma_device = {
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.name = "sh-dma-engine",
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.id = -1,
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.dev = {
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.platform_data = &dma_platform_data,
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},
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};
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static struct platform_device *sh7785_devices[] __initdata = {
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&scif0_device,
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&scif1_device,
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@ -307,6 +320,7 @@ static struct platform_device *sh7785_devices[] __initdata = {
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&tmu3_device,
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&tmu4_device,
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&tmu5_device,
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&dma_device,
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};
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static int __init sh7785_devices_setup(void)
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@ -62,6 +62,7 @@ void default_idle(void)
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clear_thread_flag(TIF_POLLING_NRFLAG);
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smp_mb__after_clear_bit();
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set_bl_bit();
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if (!need_resched()) {
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local_irq_enable();
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cpu_sleep();
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@ -69,6 +70,7 @@ void default_idle(void)
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local_irq_enable();
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set_thread_flag(TIF_POLLING_NRFLAG);
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clear_bl_bit();
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} else
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poll_idle();
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}
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@ -133,12 +133,8 @@ void __update_cache(struct vm_area_struct *vma,
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page = pfn_to_page(pfn);
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if (pfn_valid(pfn)) {
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int dirty = test_and_clear_bit(PG_dcache_dirty, &page->flags);
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if (dirty) {
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unsigned long addr = (unsigned long)page_address(page);
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if (pages_do_alias(addr, address & PAGE_MASK))
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__flush_purge_region((void *)addr, PAGE_SIZE);
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}
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if (dirty)
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__flush_purge_region(page_address(page), PAGE_SIZE);
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}
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}
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@ -222,9 +222,9 @@ static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
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Set SCP6MD1,0 = {01} (output) */
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__raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
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data = ctrl_inb(SCPDR);
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data = __raw_readb(SCPDR);
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/* Set /RTS2 (bit6) = 0 */
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ctrl_outb(data & 0xbf, SCPDR);
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__raw_writeb(data & 0xbf, SCPDR);
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}
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}
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#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
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@ -897,11 +897,21 @@ static void sci_shutdown(struct uart_port *port)
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static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
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struct ktermios *old)
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{
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unsigned int status, baud, smr_val;
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unsigned int status, baud, smr_val, max_baud;
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int t = -1;
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baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
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if (likely(baud))
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/*
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* earlyprintk comes here early on with port->uartclk set to zero.
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* the clock framework is not up and running at this point so here
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* we assume that 115200 is the maximum baud rate. please note that
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* the baud rate is not programmed during earlyprintk - it is assumed
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* that the previous boot loader has enabled required clocks and
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* setup the baud rate generator hardware for us already.
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*/
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max_baud = port->uartclk ? port->uartclk / 16 : 115200;
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baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
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if (likely(baud && port->uartclk))
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t = SCBRR_VALUE(baud, port->uartclk);
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do {
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@ -517,20 +517,20 @@ static const struct __attribute__((packed)) {
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static inline int sci_rxd_in(struct uart_port *port)
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{
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if (port->mapbase == 0xfffffe80)
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return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */
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return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */
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if (port->mapbase == 0xa4000150)
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return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
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return __raw_readb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
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if (port->mapbase == 0xa4000140)
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return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
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return __raw_readb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
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return 1;
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}
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#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
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static inline int sci_rxd_in(struct uart_port *port)
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{
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if (port->mapbase == SCIF0)
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return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
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return __raw_readb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
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if (port->mapbase == SCIF2)
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return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
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return __raw_readb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
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return 1;
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}
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#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
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@ -557,68 +557,68 @@ static inline int sci_rxd_in(struct uart_port *port)
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static inline int sci_rxd_in(struct uart_port *port)
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{
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if (port->mapbase == 0xffe00000)
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return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
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return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
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if (port->mapbase == 0xffe80000)
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return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
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return __raw_readw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
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return 1;
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}
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#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
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static inline int sci_rxd_in(struct uart_port *port)
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{
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if (port->mapbase == 0xffe80000)
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return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
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return __raw_readw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
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return 1;
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}
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#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
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static inline int sci_rxd_in(struct uart_port *port)
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{
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if (port->mapbase == 0xfe4b0000)
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return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0;
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return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0;
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if (port->mapbase == 0xfe4c0000)
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return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0;
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return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0;
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if (port->mapbase == 0xfe4d0000)
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return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0;
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return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0;
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}
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#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
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static inline int sci_rxd_in(struct uart_port *port)
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{
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if (port->mapbase == 0xfe600000)
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return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
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return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
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if (port->mapbase == 0xfe610000)
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return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
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return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
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if (port->mapbase == 0xfe620000)
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return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
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return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
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return 1;
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}
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#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
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static inline int sci_rxd_in(struct uart_port *port)
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{
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if (port->mapbase == 0xffe00000)
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return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
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return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
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if (port->mapbase == 0xffe10000)
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return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
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return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
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if (port->mapbase == 0xffe20000)
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return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
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return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
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if (port->mapbase == 0xffe30000)
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return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
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return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
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return 1;
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}
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#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
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static inline int sci_rxd_in(struct uart_port *port)
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{
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if (port->mapbase == 0xffe00000)
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return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
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return __raw_readb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
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return 1;
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}
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#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
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static inline int sci_rxd_in(struct uart_port *port)
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{
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if (port->mapbase == 0xffe00000)
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return ctrl_inb(PSDR) & 0x02 ? 1 : 0; /* SCIF0 */
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return __raw_readb(PSDR) & 0x02 ? 1 : 0; /* SCIF0 */
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if (port->mapbase == 0xffe10000)
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return ctrl_inb(PADR) & 0x40 ? 1 : 0; /* SCIF1 */
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return __raw_readb(PADR) & 0x40 ? 1 : 0; /* SCIF1 */
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if (port->mapbase == 0xffe20000)
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return ctrl_inb(PWDR) & 0x04 ? 1 : 0; /* SCIF2 */
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return __raw_readb(PWDR) & 0x04 ? 1 : 0; /* SCIF2 */
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return 1;
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}
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@ -626,17 +626,17 @@ static inline int sci_rxd_in(struct uart_port *port)
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static inline int sci_rxd_in(struct uart_port *port)
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{
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if (port->mapbase == 0xffe00000)
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return ctrl_inb(SCSPTR0) & 0x0008 ? 1 : 0; /* SCIF0 */
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return __raw_readb(SCSPTR0) & 0x0008 ? 1 : 0; /* SCIF0 */
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if (port->mapbase == 0xffe10000)
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return ctrl_inb(SCSPTR1) & 0x0020 ? 1 : 0; /* SCIF1 */
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return __raw_readb(SCSPTR1) & 0x0020 ? 1 : 0; /* SCIF1 */
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if (port->mapbase == 0xffe20000)
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return ctrl_inb(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF2 */
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return __raw_readb(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF2 */
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if (port->mapbase == 0xa4e30000)
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return ctrl_inb(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF3 */
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return __raw_readb(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF3 */
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if (port->mapbase == 0xa4e40000)
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return ctrl_inb(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF4 */
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return __raw_readb(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF4 */
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if (port->mapbase == 0xa4e50000)
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return ctrl_inb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */
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return __raw_readb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */
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return 1;
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}
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#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
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@ -645,9 +645,9 @@ static inline int sci_rxd_in(struct uart_port *port)
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static inline int sci_rxd_in(struct uart_port *port)
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{
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if (port->type == PORT_SCIF)
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return ctrl_inw((port->mapbase + SCFSR)) & SCIF_BRK ? 1 : 0;
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return __raw_readw((port->mapbase + SCFSR)) & SCIF_BRK ? 1 : 0;
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if (port->type == PORT_SCIFA)
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return ctrl_inw((port->mapbase + SCASSR)) & SCIF_BRK ? 1 : 0;
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return __raw_readw((port->mapbase + SCASSR)) & SCIF_BRK ? 1 : 0;
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return 1;
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}
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#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
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@ -665,11 +665,11 @@ static inline int sci_rxd_in(struct uart_port *port)
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static inline int sci_rxd_in(struct uart_port *port)
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{
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if (port->mapbase == 0xffe00000)
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return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
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return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
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if (port->mapbase == 0xffe08000)
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return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
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return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
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if (port->mapbase == 0xffe10000)
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return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF/IRDA */
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return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF/IRDA */
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return 1;
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}
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@ -677,20 +677,20 @@ static inline int sci_rxd_in(struct uart_port *port)
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static inline int sci_rxd_in(struct uart_port *port)
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{
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if (port->mapbase == 0xff923000)
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return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
if (port->mapbase == 0xff924000)
|
||||
return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
if (port->mapbase == 0xff925000)
|
||||
return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return 1;
|
||||
}
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
|
||||
static inline int sci_rxd_in(struct uart_port *port)
|
||||
{
|
||||
if (port->mapbase == 0xffe00000)
|
||||
return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
if (port->mapbase == 0xffe10000)
|
||||
return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return 1;
|
||||
}
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \
|
||||
|
|
@ -698,17 +698,17 @@ static inline int sci_rxd_in(struct uart_port *port)
|
|||
static inline int sci_rxd_in(struct uart_port *port)
|
||||
{
|
||||
if (port->mapbase == 0xffea0000)
|
||||
return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
if (port->mapbase == 0xffeb0000)
|
||||
return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
if (port->mapbase == 0xffec0000)
|
||||
return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
if (port->mapbase == 0xffed0000)
|
||||
return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
if (port->mapbase == 0xffee0000)
|
||||
return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return __raw_readw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
if (port->mapbase == 0xffef0000)
|
||||
return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return __raw_readw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return 1;
|
||||
}
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
|
||||
|
|
@ -718,22 +718,22 @@ static inline int sci_rxd_in(struct uart_port *port)
|
|||
static inline int sci_rxd_in(struct uart_port *port)
|
||||
{
|
||||
if (port->mapbase == 0xfffe8000)
|
||||
return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
if (port->mapbase == 0xfffe8800)
|
||||
return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
if (port->mapbase == 0xfffe9000)
|
||||
return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
if (port->mapbase == 0xfffe9800)
|
||||
return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7201)
|
||||
if (port->mapbase == 0xfffeA000)
|
||||
return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
if (port->mapbase == 0xfffeA800)
|
||||
return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
if (port->mapbase == 0xfffeB000)
|
||||
return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
if (port->mapbase == 0xfffeB800)
|
||||
return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
#endif
|
||||
return 1;
|
||||
}
|
||||
|
|
@ -741,24 +741,24 @@ static inline int sci_rxd_in(struct uart_port *port)
|
|||
static inline int sci_rxd_in(struct uart_port *port)
|
||||
{
|
||||
if (port->mapbase == 0xf8400000)
|
||||
return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
if (port->mapbase == 0xf8410000)
|
||||
return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
if (port->mapbase == 0xf8420000)
|
||||
return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return 1;
|
||||
}
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
|
||||
static inline int sci_rxd_in(struct uart_port *port)
|
||||
{
|
||||
if (port->mapbase == 0xffc30000)
|
||||
return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
if (port->mapbase == 0xffc40000)
|
||||
return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
if (port->mapbase == 0xffc50000)
|
||||
return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
if (port->mapbase == 0xffc60000)
|
||||
return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return 1;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue