mirror of
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[SCSI] hpsa: add driver for HP Smart Array controllers.
This driver supports a subset of HP Smart Array Controllers. It is a SCSI alternative to the cciss driver. [akpm@linux-foundation.org: avoid helpful cleanup patches] [achiang@hp.com: make device attrs static] [akpm@linux-foundation.org: msleep() does set_current_state() itself] Signed-off-by: Stephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: Mike Miller <mikem@beardog.cce.hp.com> Signed-off-by: Alex Chiang <achiang@hp.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: James Bottomley <James.Bottomley@suse.de>
This commit is contained in:
Stephen M. Cameron
James Bottomley
parent
0109abffbf
commit
edd163687e
5 changed files with 4141 additions and 0 deletions
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@ -388,6 +388,16 @@ config BLK_DEV_3W_XXXX_RAID
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Please read the comments at the top of
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Please read the comments at the top of
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<file:drivers/scsi/3w-xxxx.c>.
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<file:drivers/scsi/3w-xxxx.c>.
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config SCSI_HPSA
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tristate "HP Smart Array SCSI driver"
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depends on PCI && SCSI
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help
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This driver supports HP Smart Array Controllers (circa 2009).
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It is a SCSI alternative to the cciss driver, which is a block
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driver. Anyone wishing to use HP Smart Array controllers who
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would prefer the devices be presented to linux as SCSI devices,
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rather than as generic block devices should say Y here.
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config SCSI_3W_9XXX
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config SCSI_3W_9XXX
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tristate "3ware 9xxx SATA-RAID support"
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tristate "3ware 9xxx SATA-RAID support"
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depends on PCI && SCSI
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depends on PCI && SCSI
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@ -91,6 +91,7 @@ obj-$(CONFIG_SCSI_BFA_FC) += bfa/
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obj-$(CONFIG_SCSI_PAS16) += pas16.o
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obj-$(CONFIG_SCSI_PAS16) += pas16.o
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obj-$(CONFIG_SCSI_T128) += t128.o
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obj-$(CONFIG_SCSI_T128) += t128.o
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obj-$(CONFIG_SCSI_DMX3191D) += dmx3191d.o
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obj-$(CONFIG_SCSI_DMX3191D) += dmx3191d.o
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obj-$(CONFIG_SCSI_HPSA) += hpsa.o
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obj-$(CONFIG_SCSI_DTC3280) += dtc.o
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obj-$(CONFIG_SCSI_DTC3280) += dtc.o
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obj-$(CONFIG_SCSI_SYM53C8XX_2) += sym53c8xx_2/
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obj-$(CONFIG_SCSI_SYM53C8XX_2) += sym53c8xx_2/
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obj-$(CONFIG_SCSI_ZALON) += zalon7xx.o
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obj-$(CONFIG_SCSI_ZALON) += zalon7xx.o
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3531
drivers/scsi/hpsa.c
Normal file
3531
drivers/scsi/hpsa.c
Normal file
File diff suppressed because it is too large
Load diff
273
drivers/scsi/hpsa.h
Normal file
273
drivers/scsi/hpsa.h
Normal file
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@ -0,0 +1,273 @@
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/*
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* Disk Array driver for HP Smart Array SAS controllers
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* Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* Questions/Comments/Bugfixes to iss_storagedev@hp.com
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*
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*/
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#ifndef HPSA_H
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#define HPSA_H
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#include <scsi/scsicam.h>
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#define IO_OK 0
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#define IO_ERROR 1
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struct ctlr_info;
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struct access_method {
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void (*submit_command)(struct ctlr_info *h,
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struct CommandList *c);
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void (*set_intr_mask)(struct ctlr_info *h, unsigned long val);
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unsigned long (*fifo_full)(struct ctlr_info *h);
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unsigned long (*intr_pending)(struct ctlr_info *h);
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unsigned long (*command_completed)(struct ctlr_info *h);
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};
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struct hpsa_scsi_dev_t {
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int devtype;
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int bus, target, lun; /* as presented to the OS */
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unsigned char scsi3addr[8]; /* as presented to the HW */
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#define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
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unsigned char device_id[16]; /* from inquiry pg. 0x83 */
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unsigned char vendor[8]; /* bytes 8-15 of inquiry data */
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unsigned char model[16]; /* bytes 16-31 of inquiry data */
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unsigned char revision[4]; /* bytes 32-35 of inquiry data */
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unsigned char raid_level; /* from inquiry page 0xC1 */
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};
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struct ctlr_info {
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int ctlr;
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char devname[8];
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char *product_name;
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char firm_ver[4]; /* Firmware version */
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struct pci_dev *pdev;
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__u32 board_id;
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void __iomem *vaddr;
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unsigned long paddr;
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int nr_cmds; /* Number of commands allowed on this controller */
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struct CfgTable __iomem *cfgtable;
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int interrupts_enabled;
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int major;
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int max_commands;
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int commands_outstanding;
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int max_outstanding; /* Debug */
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int usage_count; /* number of opens all all minor devices */
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# define DOORBELL_INT 0
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# define PERF_MODE_INT 1
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# define SIMPLE_MODE_INT 2
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# define MEMQ_MODE_INT 3
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unsigned int intr[4];
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unsigned int msix_vector;
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unsigned int msi_vector;
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struct access_method access;
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/* queue and queue Info */
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struct hlist_head reqQ;
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struct hlist_head cmpQ;
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unsigned int Qdepth;
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unsigned int maxQsinceinit;
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unsigned int maxSG;
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spinlock_t lock;
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/* pointers to command and error info pool */
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struct CommandList *cmd_pool;
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dma_addr_t cmd_pool_dhandle;
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struct ErrorInfo *errinfo_pool;
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dma_addr_t errinfo_pool_dhandle;
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unsigned long *cmd_pool_bits;
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int nr_allocs;
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int nr_frees;
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int busy_initializing;
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int busy_scanning;
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struct mutex busy_shutting_down;
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struct list_head scan_list;
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struct completion scan_wait;
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struct Scsi_Host *scsi_host;
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spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */
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int ndevices; /* number of used elements in .dev[] array. */
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#define HPSA_MAX_SCSI_DEVS_PER_HBA 256
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struct hpsa_scsi_dev_t *dev[HPSA_MAX_SCSI_DEVS_PER_HBA];
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};
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#define HPSA_ABORT_MSG 0
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#define HPSA_DEVICE_RESET_MSG 1
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#define HPSA_BUS_RESET_MSG 2
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#define HPSA_HOST_RESET_MSG 3
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#define HPSA_MSG_SEND_RETRY_LIMIT 10
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#define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS 1000
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/* Maximum time in seconds driver will wait for command completions
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* when polling before giving up.
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*/
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#define HPSA_MAX_POLL_TIME_SECS (20)
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/* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
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* how many times to retry TEST UNIT READY on a device
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* while waiting for it to become ready before giving up.
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* HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
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* between sending TURs while waiting for a device
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* to become ready.
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*/
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#define HPSA_TUR_RETRY_LIMIT (20)
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#define HPSA_MAX_WAIT_INTERVAL_SECS (30)
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/* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
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* to become ready, in seconds, before giving up on it.
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* HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
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* between polling the board to see if it is ready, in
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* milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and
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* HPSA_BOARD_READY_ITERATIONS are derived from those.
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*/
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#define HPSA_BOARD_READY_WAIT_SECS (120)
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#define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
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#define HPSA_BOARD_READY_POLL_INTERVAL \
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((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
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#define HPSA_BOARD_READY_ITERATIONS \
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((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
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HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
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#define HPSA_POST_RESET_PAUSE_MSECS (3000)
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#define HPSA_POST_RESET_NOOP_RETRIES (12)
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/* Defining the diffent access_menthods */
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/*
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* Memory mapped FIFO interface (SMART 53xx cards)
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*/
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#define SA5_DOORBELL 0x20
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#define SA5_REQUEST_PORT_OFFSET 0x40
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#define SA5_REPLY_INTR_MASK_OFFSET 0x34
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#define SA5_REPLY_PORT_OFFSET 0x44
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#define SA5_INTR_STATUS 0x30
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#define SA5_SCRATCHPAD_OFFSET 0xB0
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#define SA5_CTCFG_OFFSET 0xB4
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#define SA5_CTMEM_OFFSET 0xB8
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#define SA5_INTR_OFF 0x08
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#define SA5B_INTR_OFF 0x04
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#define SA5_INTR_PENDING 0x08
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#define SA5B_INTR_PENDING 0x04
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#define FIFO_EMPTY 0xffffffff
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#define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
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#define HPSA_ERROR_BIT 0x02
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#define HPSA_TAG_CONTAINS_INDEX(tag) ((tag) & 0x04)
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#define HPSA_TAG_TO_INDEX(tag) ((tag) >> 3)
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#define HPSA_TAG_DISCARD_ERROR_BITS(tag) ((tag) & ~3)
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#define HPSA_INTR_ON 1
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#define HPSA_INTR_OFF 0
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/*
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Send the command to the hardware
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*/
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static void SA5_submit_command(struct ctlr_info *h,
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struct CommandList *c)
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{
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#ifdef HPSA_DEBUG
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printk(KERN_WARNING "hpsa: Sending %x - down to controller\n",
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c->busaddr);
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#endif /* HPSA_DEBUG */
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writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
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h->commands_outstanding++;
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if (h->commands_outstanding > h->max_outstanding)
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h->max_outstanding = h->commands_outstanding;
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}
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/*
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* This card is the opposite of the other cards.
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* 0 turns interrupts on...
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* 0x08 turns them off...
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*/
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static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
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{
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if (val) { /* Turn interrupts on */
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h->interrupts_enabled = 1;
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writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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} else { /* Turn them off */
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h->interrupts_enabled = 0;
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writel(SA5_INTR_OFF,
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h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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}
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}
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/*
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* Returns true if fifo is full.
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*
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*/
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static unsigned long SA5_fifo_full(struct ctlr_info *h)
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{
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if (h->commands_outstanding >= h->max_commands)
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return 1;
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else
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return 0;
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}
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/*
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* returns value read from hardware.
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* returns FIFO_EMPTY if there is nothing to read
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*/
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static unsigned long SA5_completed(struct ctlr_info *h)
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{
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unsigned long register_value
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= readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
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if (register_value != FIFO_EMPTY)
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h->commands_outstanding--;
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#ifdef HPSA_DEBUG
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if (register_value != FIFO_EMPTY)
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printk(KERN_INFO "hpsa: Read %lx back from board\n",
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register_value);
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else
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printk(KERN_INFO "hpsa: FIFO Empty read\n");
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#endif
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return register_value;
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}
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/*
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* Returns true if an interrupt is pending..
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*/
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static unsigned long SA5_intr_pending(struct ctlr_info *h)
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{
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unsigned long register_value =
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readl(h->vaddr + SA5_INTR_STATUS);
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#ifdef HPSA_DEBUG
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printk(KERN_INFO "hpsa: intr_pending %lx\n", register_value);
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#endif /* HPSA_DEBUG */
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if (register_value & SA5_INTR_PENDING)
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return 1;
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return 0 ;
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}
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static struct access_method SA5_access = {
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SA5_submit_command,
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SA5_intr_mask,
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SA5_fifo_full,
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SA5_intr_pending,
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SA5_completed,
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};
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struct board_type {
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__u32 board_id;
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char *product_name;
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struct access_method *access;
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};
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/* end of old hpsa_scsi.h file */
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#endif /* HPSA_H */
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326
drivers/scsi/hpsa_cmd.h
Normal file
326
drivers/scsi/hpsa_cmd.h
Normal file
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@ -0,0 +1,326 @@
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/*
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* Disk Array driver for HP Smart Array SAS controllers
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* Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
|
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*
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* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
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||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||||
|
* NON INFRINGEMENT. See the GNU General Public License for more details.
|
||||||
|
*
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|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||||
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*
|
||||||
|
* Questions/Comments/Bugfixes to iss_storagedev@hp.com
|
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*
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*/
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#ifndef HPSA_CMD_H
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#define HPSA_CMD_H
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/* general boundary defintions */
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#define SENSEINFOBYTES 32 /* may vary between hbas */
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#define MAXSGENTRIES 31
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#define MAXREPLYQS 256
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/* Command Status value */
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#define CMD_SUCCESS 0x0000
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#define CMD_TARGET_STATUS 0x0001
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#define CMD_DATA_UNDERRUN 0x0002
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#define CMD_DATA_OVERRUN 0x0003
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#define CMD_INVALID 0x0004
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#define CMD_PROTOCOL_ERR 0x0005
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#define CMD_HARDWARE_ERR 0x0006
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#define CMD_CONNECTION_LOST 0x0007
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#define CMD_ABORTED 0x0008
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||||||
|
#define CMD_ABORT_FAILED 0x0009
|
||||||
|
#define CMD_UNSOLICITED_ABORT 0x000A
|
||||||
|
#define CMD_TIMEOUT 0x000B
|
||||||
|
#define CMD_UNABORTABLE 0x000C
|
||||||
|
|
||||||
|
/* Unit Attentions ASC's as defined for the MSA2012sa */
|
||||||
|
#define POWER_OR_RESET 0x29
|
||||||
|
#define STATE_CHANGED 0x2a
|
||||||
|
#define UNIT_ATTENTION_CLEARED 0x2f
|
||||||
|
#define LUN_FAILED 0x3e
|
||||||
|
#define REPORT_LUNS_CHANGED 0x3f
|
||||||
|
|
||||||
|
/* Unit Attentions ASCQ's as defined for the MSA2012sa */
|
||||||
|
|
||||||
|
/* These ASCQ's defined for ASC = POWER_OR_RESET */
|
||||||
|
#define POWER_ON_RESET 0x00
|
||||||
|
#define POWER_ON_REBOOT 0x01
|
||||||
|
#define SCSI_BUS_RESET 0x02
|
||||||
|
#define MSA_TARGET_RESET 0x03
|
||||||
|
#define CONTROLLER_FAILOVER 0x04
|
||||||
|
#define TRANSCEIVER_SE 0x05
|
||||||
|
#define TRANSCEIVER_LVD 0x06
|
||||||
|
|
||||||
|
/* These ASCQ's defined for ASC = STATE_CHANGED */
|
||||||
|
#define RESERVATION_PREEMPTED 0x03
|
||||||
|
#define ASYM_ACCESS_CHANGED 0x06
|
||||||
|
#define LUN_CAPACITY_CHANGED 0x09
|
||||||
|
|
||||||
|
/* transfer direction */
|
||||||
|
#define XFER_NONE 0x00
|
||||||
|
#define XFER_WRITE 0x01
|
||||||
|
#define XFER_READ 0x02
|
||||||
|
#define XFER_RSVD 0x03
|
||||||
|
|
||||||
|
/* task attribute */
|
||||||
|
#define ATTR_UNTAGGED 0x00
|
||||||
|
#define ATTR_SIMPLE 0x04
|
||||||
|
#define ATTR_HEADOFQUEUE 0x05
|
||||||
|
#define ATTR_ORDERED 0x06
|
||||||
|
#define ATTR_ACA 0x07
|
||||||
|
|
||||||
|
/* cdb type */
|
||||||
|
#define TYPE_CMD 0x00
|
||||||
|
#define TYPE_MSG 0x01
|
||||||
|
|
||||||
|
/* config space register offsets */
|
||||||
|
#define CFG_VENDORID 0x00
|
||||||
|
#define CFG_DEVICEID 0x02
|
||||||
|
#define CFG_I2OBAR 0x10
|
||||||
|
#define CFG_MEM1BAR 0x14
|
||||||
|
|
||||||
|
/* i2o space register offsets */
|
||||||
|
#define I2O_IBDB_SET 0x20
|
||||||
|
#define I2O_IBDB_CLEAR 0x70
|
||||||
|
#define I2O_INT_STATUS 0x30
|
||||||
|
#define I2O_INT_MASK 0x34
|
||||||
|
#define I2O_IBPOST_Q 0x40
|
||||||
|
#define I2O_OBPOST_Q 0x44
|
||||||
|
#define I2O_DMA1_CFG 0x214
|
||||||
|
|
||||||
|
/* Configuration Table */
|
||||||
|
#define CFGTBL_ChangeReq 0x00000001l
|
||||||
|
#define CFGTBL_AccCmds 0x00000001l
|
||||||
|
|
||||||
|
#define CFGTBL_Trans_Simple 0x00000002l
|
||||||
|
|
||||||
|
#define CFGTBL_BusType_Ultra2 0x00000001l
|
||||||
|
#define CFGTBL_BusType_Ultra3 0x00000002l
|
||||||
|
#define CFGTBL_BusType_Fibre1G 0x00000100l
|
||||||
|
#define CFGTBL_BusType_Fibre2G 0x00000200l
|
||||||
|
struct vals32 {
|
||||||
|
__u32 lower;
|
||||||
|
__u32 upper;
|
||||||
|
};
|
||||||
|
|
||||||
|
union u64bit {
|
||||||
|
struct vals32 val32;
|
||||||
|
__u64 val;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* FIXME this is a per controller value (barf!) */
|
||||||
|
#define HPSA_MAX_TARGETS_PER_CTLR 16
|
||||||
|
#define HPSA_MAX_LUN 256
|
||||||
|
#define HPSA_MAX_PHYS_LUN 1024
|
||||||
|
|
||||||
|
/* SCSI-3 Commands */
|
||||||
|
#pragma pack(1)
|
||||||
|
|
||||||
|
#define HPSA_INQUIRY 0x12
|
||||||
|
struct InquiryData {
|
||||||
|
__u8 data_byte[36];
|
||||||
|
};
|
||||||
|
|
||||||
|
#define HPSA_REPORT_LOG 0xc2 /* Report Logical LUNs */
|
||||||
|
#define HPSA_REPORT_PHYS 0xc3 /* Report Physical LUNs */
|
||||||
|
struct ReportLUNdata {
|
||||||
|
__u8 LUNListLength[4];
|
||||||
|
__u32 reserved;
|
||||||
|
__u8 LUN[HPSA_MAX_LUN][8];
|
||||||
|
};
|
||||||
|
|
||||||
|
struct ReportExtendedLUNdata {
|
||||||
|
__u8 LUNListLength[4];
|
||||||
|
__u8 extended_response_flag;
|
||||||
|
__u8 reserved[3];
|
||||||
|
__u8 LUN[HPSA_MAX_LUN][24];
|
||||||
|
};
|
||||||
|
|
||||||
|
struct SenseSubsystem_info {
|
||||||
|
__u8 reserved[36];
|
||||||
|
__u8 portname[8];
|
||||||
|
__u8 reserved1[1108];
|
||||||
|
};
|
||||||
|
|
||||||
|
#define HPSA_READ_CAPACITY 0x25 /* Read Capacity */
|
||||||
|
struct ReadCapdata {
|
||||||
|
__u8 total_size[4]; /* Total size in blocks */
|
||||||
|
__u8 block_size[4]; /* Size of blocks in bytes */
|
||||||
|
};
|
||||||
|
|
||||||
|
#if 0
|
||||||
|
/* 12 byte commands not implemented in firmware yet. */
|
||||||
|
#define HPSA_READ 0xa8
|
||||||
|
#define HPSA_WRITE 0xaa
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define HPSA_READ 0x28 /* Read(10) */
|
||||||
|
#define HPSA_WRITE 0x2a /* Write(10) */
|
||||||
|
|
||||||
|
/* BMIC commands */
|
||||||
|
#define BMIC_READ 0x26
|
||||||
|
#define BMIC_WRITE 0x27
|
||||||
|
#define BMIC_CACHE_FLUSH 0xc2
|
||||||
|
#define HPSA_CACHE_FLUSH 0x01 /* C2 was already being used by HPSA */
|
||||||
|
|
||||||
|
/* Command List Structure */
|
||||||
|
union SCSI3Addr {
|
||||||
|
struct {
|
||||||
|
__u8 Dev;
|
||||||
|
__u8 Bus:6;
|
||||||
|
__u8 Mode:2; /* b00 */
|
||||||
|
} PeripDev;
|
||||||
|
struct {
|
||||||
|
__u8 DevLSB;
|
||||||
|
__u8 DevMSB:6;
|
||||||
|
__u8 Mode:2; /* b01 */
|
||||||
|
} LogDev;
|
||||||
|
struct {
|
||||||
|
__u8 Dev:5;
|
||||||
|
__u8 Bus:3;
|
||||||
|
__u8 Targ:6;
|
||||||
|
__u8 Mode:2; /* b10 */
|
||||||
|
} LogUnit;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct PhysDevAddr {
|
||||||
|
__u32 TargetId:24;
|
||||||
|
__u32 Bus:6;
|
||||||
|
__u32 Mode:2;
|
||||||
|
/* 2 level target device addr */
|
||||||
|
union SCSI3Addr Target[2];
|
||||||
|
};
|
||||||
|
|
||||||
|
struct LogDevAddr {
|
||||||
|
__u32 VolId:30;
|
||||||
|
__u32 Mode:2;
|
||||||
|
__u8 reserved[4];
|
||||||
|
};
|
||||||
|
|
||||||
|
union LUNAddr {
|
||||||
|
__u8 LunAddrBytes[8];
|
||||||
|
union SCSI3Addr SCSI3Lun[4];
|
||||||
|
struct PhysDevAddr PhysDev;
|
||||||
|
struct LogDevAddr LogDev;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct CommandListHeader {
|
||||||
|
__u8 ReplyQueue;
|
||||||
|
__u8 SGList;
|
||||||
|
__u16 SGTotal;
|
||||||
|
struct vals32 Tag;
|
||||||
|
union LUNAddr LUN;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct RequestBlock {
|
||||||
|
__u8 CDBLen;
|
||||||
|
struct {
|
||||||
|
__u8 Type:3;
|
||||||
|
__u8 Attribute:3;
|
||||||
|
__u8 Direction:2;
|
||||||
|
} Type;
|
||||||
|
__u16 Timeout;
|
||||||
|
__u8 CDB[16];
|
||||||
|
};
|
||||||
|
|
||||||
|
struct ErrDescriptor {
|
||||||
|
struct vals32 Addr;
|
||||||
|
__u32 Len;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct SGDescriptor {
|
||||||
|
struct vals32 Addr;
|
||||||
|
__u32 Len;
|
||||||
|
__u32 Ext;
|
||||||
|
};
|
||||||
|
|
||||||
|
union MoreErrInfo {
|
||||||
|
struct {
|
||||||
|
__u8 Reserved[3];
|
||||||
|
__u8 Type;
|
||||||
|
__u32 ErrorInfo;
|
||||||
|
} Common_Info;
|
||||||
|
struct {
|
||||||
|
__u8 Reserved[2];
|
||||||
|
__u8 offense_size; /* size of offending entry */
|
||||||
|
__u8 offense_num; /* byte # of offense 0-base */
|
||||||
|
__u32 offense_value;
|
||||||
|
} Invalid_Cmd;
|
||||||
|
};
|
||||||
|
struct ErrorInfo {
|
||||||
|
__u8 ScsiStatus;
|
||||||
|
__u8 SenseLen;
|
||||||
|
__u16 CommandStatus;
|
||||||
|
__u32 ResidualCnt;
|
||||||
|
union MoreErrInfo MoreErrInfo;
|
||||||
|
__u8 SenseInfo[SENSEINFOBYTES];
|
||||||
|
};
|
||||||
|
/* Command types */
|
||||||
|
#define CMD_IOCTL_PEND 0x01
|
||||||
|
#define CMD_SCSI 0x03
|
||||||
|
|
||||||
|
struct ctlr_info; /* defined in hpsa.h */
|
||||||
|
/* The size of this structure needs to be divisible by 8
|
||||||
|
* od on all architectures, because the controller uses 2
|
||||||
|
* lower bits of the address, and the driver uses 1 lower
|
||||||
|
* bit (3 bits total.)
|
||||||
|
*/
|
||||||
|
struct CommandList {
|
||||||
|
struct CommandListHeader Header;
|
||||||
|
struct RequestBlock Request;
|
||||||
|
struct ErrDescriptor ErrDesc;
|
||||||
|
struct SGDescriptor SG[MAXSGENTRIES];
|
||||||
|
/* information associated with the command */
|
||||||
|
__u32 busaddr; /* physical addr of this record */
|
||||||
|
struct ErrorInfo *err_info; /* pointer to the allocated mem */
|
||||||
|
struct ctlr_info *h;
|
||||||
|
int cmd_type;
|
||||||
|
long cmdindex;
|
||||||
|
struct hlist_node list;
|
||||||
|
struct CommandList *prev;
|
||||||
|
struct CommandList *next;
|
||||||
|
struct request *rq;
|
||||||
|
struct completion *waiting;
|
||||||
|
int retry_count;
|
||||||
|
void *scsi_cmd;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* Configuration Table Structure */
|
||||||
|
struct HostWrite {
|
||||||
|
__u32 TransportRequest;
|
||||||
|
__u32 Reserved;
|
||||||
|
__u32 CoalIntDelay;
|
||||||
|
__u32 CoalIntCount;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct CfgTable {
|
||||||
|
__u8 Signature[4];
|
||||||
|
__u32 SpecValence;
|
||||||
|
__u32 TransportSupport;
|
||||||
|
__u32 TransportActive;
|
||||||
|
struct HostWrite HostWrite;
|
||||||
|
__u32 CmdsOutMax;
|
||||||
|
__u32 BusTypes;
|
||||||
|
__u32 Reserved;
|
||||||
|
__u8 ServerName[16];
|
||||||
|
__u32 HeartBeat;
|
||||||
|
__u32 SCSI_Prefetch;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct hpsa_pci_info {
|
||||||
|
unsigned char bus;
|
||||||
|
unsigned char dev_fn;
|
||||||
|
unsigned short domain;
|
||||||
|
__u32 board_id;
|
||||||
|
};
|
||||||
|
|
||||||
|
#pragma pack()
|
||||||
|
#endif /* HPSA_CMD_H */
|
||||||
Loading…
Reference in a new issue