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Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86: fix resume (S2R) broken by Intel microcode module, on A110L x86 gart: don't complain if no AMD GART found AMD IOMMU: panic if completion wait loop fails AMD IOMMU: set cmd buffer pointers to zero manually x86: re-enable MCE on secondary CPUS after suspend/resume AMD IOMMU: allocate rlookup_table with __GFP_ZERO
This commit is contained in:
commit
e6a997eda9
6 changed files with 30 additions and 14 deletions
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@ -235,8 +235,9 @@ static int iommu_completion_wait(struct amd_iommu *iommu)
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status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
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writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
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if (unlikely((i == EXIT_LOOP_COUNT) && printk_ratelimit()))
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printk(KERN_WARNING "AMD IOMMU: Completion wait loop failed\n");
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if (unlikely(i == EXIT_LOOP_COUNT))
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panic("AMD IOMMU: Completion wait loop failed\n");
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out:
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spin_unlock_irqrestore(&iommu->lock, flags);
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@ -427,6 +427,10 @@ static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
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memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
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&entry, sizeof(entry));
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/* set head and tail to zero manually */
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writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
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writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
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iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
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return cmd_buf;
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@ -1074,7 +1078,8 @@ int __init amd_iommu_init(void)
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goto free;
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/* IOMMU rlookup table - find the IOMMU for a specific device */
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amd_iommu_rlookup_table = (void *)__get_free_pages(GFP_KERNEL,
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amd_iommu_rlookup_table = (void *)__get_free_pages(
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GFP_KERNEL | __GFP_ZERO,
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get_order(rlookup_table_size));
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if (amd_iommu_rlookup_table == NULL)
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goto free;
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@ -510,12 +510,9 @@ static void __cpuinit mce_cpu_features(struct cpuinfo_x86 *c)
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*/
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void __cpuinit mcheck_init(struct cpuinfo_x86 *c)
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{
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static cpumask_t mce_cpus = CPU_MASK_NONE;
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mce_cpu_quirks(c);
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if (mce_dont_init ||
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cpu_test_and_set(smp_processor_id(), mce_cpus) ||
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!mce_available(c))
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return;
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@ -272,13 +272,18 @@ static struct attribute_group mc_attr_group = {
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.name = "microcode",
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};
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static void microcode_fini_cpu(int cpu)
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static void __microcode_fini_cpu(int cpu)
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{
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struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
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mutex_lock(µcode_mutex);
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microcode_ops->microcode_fini_cpu(cpu);
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uci->valid = 0;
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}
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static void microcode_fini_cpu(int cpu)
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{
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mutex_lock(µcode_mutex);
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__microcode_fini_cpu(cpu);
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mutex_unlock(µcode_mutex);
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}
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@ -306,12 +311,16 @@ static int microcode_resume_cpu(int cpu)
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* to this cpu (a bit of paranoia):
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*/
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if (microcode_ops->collect_cpu_info(cpu, &nsig)) {
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microcode_fini_cpu(cpu);
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__microcode_fini_cpu(cpu);
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printk(KERN_ERR "failed to collect_cpu_info for resuming cpu #%d\n",
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cpu);
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return -1;
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}
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if (memcmp(&nsig, &uci->cpu_sig, sizeof(nsig))) {
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microcode_fini_cpu(cpu);
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if ((nsig.sig != uci->cpu_sig.sig) || (nsig.pf != uci->cpu_sig.pf)) {
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__microcode_fini_cpu(cpu);
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printk(KERN_ERR "cached ucode doesn't match the resuming cpu #%d\n",
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cpu);
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/* Should we look for a new ucode here? */
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return 1;
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}
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@ -155,6 +155,7 @@ static DEFINE_SPINLOCK(microcode_update_lock);
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static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
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{
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struct cpuinfo_x86 *c = &cpu_data(cpu_num);
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unsigned long flags;
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unsigned int val[2];
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memset(csig, 0, sizeof(*csig));
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@ -174,11 +175,16 @@ static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
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csig->pf = 1 << ((val[1] >> 18) & 7);
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}
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/* serialize access to the physical write to MSR 0x79 */
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spin_lock_irqsave(µcode_update_lock, flags);
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wrmsr(MSR_IA32_UCODE_REV, 0, 0);
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/* see notes above for revision 1.07. Apparent chip bug */
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sync_core();
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/* get the current revision from MSR 0x8B */
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rdmsr(MSR_IA32_UCODE_REV, val[0], csig->rev);
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spin_unlock_irqrestore(µcode_update_lock, flags);
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pr_debug("microcode: collect_cpu_info : sig=0x%x, pf=0x%x, rev=0x%x\n",
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csig->sig, csig->pf, csig->rev);
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@ -745,10 +745,8 @@ void __init gart_iommu_init(void)
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unsigned long scratch;
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long i;
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if (cache_k8_northbridges() < 0 || num_k8_northbridges == 0) {
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printk(KERN_INFO "PCI-GART: No AMD GART found.\n");
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if (cache_k8_northbridges() < 0 || num_k8_northbridges == 0)
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return;
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}
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#ifndef CONFIG_AGP_AMD64
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no_agp = 1;
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