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V4L/DVB (5675): Move big PIO accesses from the interrupt handler to a workhandler
Sliced VBI transfers use PIO instead of DMA. This was done inside the interrupt handler, but since PIO accesses are very slow this meant that a lot of time was spent inside the interrupt handler. All PIO copies are now moved to a workqueue. This should fix various issues with missing time ticks and remote key hits. Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
This commit is contained in:
Hans Verkuil
Mauro Carvalho Chehab
parent
ffeb9ec72e
commit
dc02d50a6d
7 changed files with 210 additions and 87 deletions
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@ -652,6 +652,7 @@ static int __devinit ivtv_init_struct1(struct ivtv *itv)
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itv->dma_timer.data = (unsigned long)itv;
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itv->cur_dma_stream = -1;
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itv->cur_pio_stream = -1;
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itv->audio_stereo_mode = AUDIO_STEREO;
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itv->audio_bilingual_mode = AUDIO_MONO_LEFT;
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@ -237,6 +237,7 @@ extern const u32 yuv_offset[4];
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#define IVTV_IRQ_ENC_VBI_CAP (0x1 << 29)
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#define IVTV_IRQ_ENC_VIM_RST (0x1 << 28)
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#define IVTV_IRQ_ENC_DMA_COMPLETE (0x1 << 27)
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#define IVTV_IRQ_ENC_PIO_COMPLETE (0x1 << 25)
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#define IVTV_IRQ_DEC_AUD_MODE_CHG (0x1 << 24)
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#define IVTV_IRQ_DEC_DATA_REQ (0x1 << 22)
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#define IVTV_IRQ_DEC_DMA_COMPLETE (0x1 << 20)
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@ -247,7 +248,8 @@ extern const u32 yuv_offset[4];
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#define IVTV_IRQ_DEC_VSYNC (0x1 << 10)
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/* IRQ Masks */
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#define IVTV_IRQ_MASK_INIT (IVTV_IRQ_DMA_ERR|IVTV_IRQ_ENC_DMA_COMPLETE|IVTV_IRQ_DMA_READ)
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#define IVTV_IRQ_MASK_INIT (IVTV_IRQ_DMA_ERR|IVTV_IRQ_ENC_DMA_COMPLETE|\
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IVTV_IRQ_DMA_READ|IVTV_IRQ_ENC_PIO_COMPLETE)
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#define IVTV_IRQ_MASK_CAPTURE (IVTV_IRQ_ENC_START_CAP | IVTV_IRQ_ENC_EOS)
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#define IVTV_IRQ_MASK_DECODE (IVTV_IRQ_DEC_DATA_REQ|IVTV_IRQ_DEC_AUD_MODE_CHG)
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@ -374,6 +376,9 @@ struct ivtv_mailbox_data {
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#define IVTV_F_S_STREAMOFF 7 /* signal end of stream EOS */
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#define IVTV_F_S_APPL_IO 8 /* this stream is used read/written by an application */
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#define IVTV_F_S_PIO_PENDING 9 /* this stream has pending PIO */
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#define IVTV_F_S_PIO_HAS_VBI 1 /* the current PIO request also requests VBI data */
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/* per-ivtv, i_flags */
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#define IVTV_F_I_DMA 0 /* DMA in progress */
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#define IVTV_F_I_UDMA 1 /* UDMA in progress */
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@ -390,8 +395,11 @@ struct ivtv_mailbox_data {
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#define IVTV_F_I_DECODING_YUV 12 /* this stream is YUV frame decoding */
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#define IVTV_F_I_ENC_PAUSED 13 /* the encoder is paused */
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#define IVTV_F_I_VALID_DEC_TIMINGS 14 /* last_dec_timing is valid */
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#define IVTV_F_I_WORK_HANDLER_VBI 15 /* there is work to be done for VBI */
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#define IVTV_F_I_WORK_HANDLER_YUV 16 /* there is work to be done for YUV */
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#define IVTV_F_I_HAVE_WORK 15 /* Used in the interrupt handler: there is work to be done */
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#define IVTV_F_I_WORK_HANDLER_VBI 16 /* there is work to be done for VBI */
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#define IVTV_F_I_WORK_HANDLER_YUV 17 /* there is work to be done for YUV */
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#define IVTV_F_I_WORK_HANDLER_PIO 18 /* there is work to be done for PIO */
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#define IVTV_F_I_PIO 19 /* PIO in progress */
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/* Event notifications */
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#define IVTV_F_I_EV_DEC_STOPPED 28 /* decoder stopped event */
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@ -484,6 +492,7 @@ struct ivtv_stream {
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/* Base Dev SG Array for cx23415/6 */
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struct ivtv_SG_element *SGarray;
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struct ivtv_SG_element *PIOarray;
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dma_addr_t SG_handle;
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int SG_length;
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@ -706,6 +715,7 @@ struct ivtv {
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atomic_t decoding; /* count number of active decoding streams */
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u32 irq_rr_idx; /* Round-robin stream index */
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int cur_dma_stream; /* index of stream doing DMA */
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int cur_pio_stream; /* index of stream doing PIO */
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u32 dma_data_req_offset;
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u32 dma_data_req_size;
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int output_mode; /* NONE, MPG, YUV, UDMA YUV, passthrough */
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@ -31,8 +31,6 @@
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#define DMA_MAGIC_COOKIE 0x000001fe
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#define SLICED_VBI_PIO 1
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static void ivtv_dma_dec_start(struct ivtv_stream *s);
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static const int ivtv_stream_map[] = {
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@ -42,12 +40,40 @@ static const int ivtv_stream_map[] = {
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IVTV_ENC_STREAM_TYPE_VBI,
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};
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static inline int ivtv_use_pio(struct ivtv_stream *s)
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{
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struct ivtv *itv = s->itv;
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return s->dma == PCI_DMA_NONE ||
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(SLICED_VBI_PIO && s->type == IVTV_ENC_STREAM_TYPE_VBI && itv->vbi.sliced_in->service_set);
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static void ivtv_pio_work_handler(struct ivtv *itv)
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{
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struct ivtv_stream *s = &itv->streams[itv->cur_pio_stream];
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struct ivtv_buffer *buf;
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struct list_head *p;
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int i = 0;
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IVTV_DEBUG_DMA("ivtv_pio_work_handler\n");
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if (itv->cur_pio_stream < 0 || itv->cur_pio_stream >= IVTV_MAX_STREAMS ||
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s->v4l2dev == NULL || !ivtv_use_pio(s)) {
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itv->cur_pio_stream = -1;
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/* trigger PIO complete user interrupt */
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write_reg(IVTV_IRQ_ENC_PIO_COMPLETE, 0x44);
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return;
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}
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IVTV_DEBUG_DMA("Process PIO %s\n", s->name);
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buf = list_entry(s->q_dma.list.next, struct ivtv_buffer, list);
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list_for_each(p, &s->q_dma.list) {
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struct ivtv_buffer *buf = list_entry(p, struct ivtv_buffer, list);
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u32 size = s->PIOarray[i].size & 0x3ffff;
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/* Copy the data from the card to the buffer */
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if (s->type == IVTV_DEC_STREAM_TYPE_VBI) {
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memcpy_fromio(buf->buf, itv->dec_mem + s->PIOarray[i].src - IVTV_DECODER_OFFSET, size);
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}
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else {
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memcpy_fromio(buf->buf, itv->enc_mem + s->PIOarray[i].src, size);
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}
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if (s->PIOarray[i].size & 0x80000000)
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break;
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i++;
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}
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write_reg(IVTV_IRQ_ENC_PIO_COMPLETE, 0x44);
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}
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void ivtv_irq_work_handler(struct work_struct *work)
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@ -56,8 +82,11 @@ void ivtv_irq_work_handler(struct work_struct *work)
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DEFINE_WAIT(wait);
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if (test_and_clear_bit(IVTV_F_I_WORK_HANDLER_PIO, &itv->i_flags))
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ivtv_pio_work_handler(itv);
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if (test_and_clear_bit(IVTV_F_I_WORK_HANDLER_VBI, &itv->i_flags))
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vbi_work_handler(itv);
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ivtv_vbi_work_handler(itv);
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if (test_and_clear_bit(IVTV_F_I_WORK_HANDLER_YUV, &itv->i_flags))
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ivtv_yuv_work_handler(itv);
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@ -173,8 +202,7 @@ static int stream_enc_dma_append(struct ivtv_stream *s, u32 data[CX2341X_MBOX_MA
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}
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s->buffers_stolen = rc;
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/* got the buffers, now fill in SGarray (DMA) or copy the data from the card
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to the buffers (PIO). */
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/* got the buffers, now fill in SGarray (DMA) */
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buf = list_entry(s->q_predma.list.next, struct ivtv_buffer, list);
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memset(buf->buf, 0, 128);
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list_for_each(p, &s->q_predma.list) {
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@ -182,21 +210,11 @@ static int stream_enc_dma_append(struct ivtv_stream *s, u32 data[CX2341X_MBOX_MA
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if (skip_bufs-- > 0)
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continue;
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if (!ivtv_use_pio(s)) {
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s->SGarray[idx].dst = cpu_to_le32(buf->dma_handle);
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s->SGarray[idx].src = cpu_to_le32(offset);
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s->SGarray[idx].size = cpu_to_le32(s->buf_size);
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}
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s->SGarray[idx].dst = cpu_to_le32(buf->dma_handle);
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s->SGarray[idx].src = cpu_to_le32(offset);
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s->SGarray[idx].size = cpu_to_le32(s->buf_size);
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buf->bytesused = (size < s->buf_size) ? size : s->buf_size;
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/* If PIO, then copy the data from the card to the buffer */
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if (s->type == IVTV_DEC_STREAM_TYPE_VBI) {
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memcpy_fromio(buf->buf, itv->dec_mem + offset - IVTV_DECODER_OFFSET, buf->bytesused);
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}
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else if (ivtv_use_pio(s)) {
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memcpy_fromio(buf->buf, itv->enc_mem + offset, buf->bytesused);
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}
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s->q_predma.bytesused += buf->bytesused;
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size -= buf->bytesused;
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offset += s->buf_size;
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@ -224,11 +242,6 @@ static void dma_post(struct ivtv_stream *s)
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u32 *u32buf;
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int x = 0;
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if (ivtv_use_pio(s)) {
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if (s->q_predma.bytesused)
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ivtv_queue_move(s, &s->q_predma, NULL, &s->q_dma, s->q_predma.bytesused);
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s->SG_length = 0;
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}
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IVTV_DEBUG_DMA("%s %s completed (%x)\n", ivtv_use_pio(s) ? "PIO" : "DMA",
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s->name, s->dma_offset);
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list_for_each(p, &s->q_dma.list) {
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@ -278,10 +291,14 @@ static void dma_post(struct ivtv_stream *s)
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if (buf)
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buf->bytesused += s->dma_last_offset;
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if (buf && s->type == IVTV_DEC_STREAM_TYPE_VBI) {
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/* Parse and Groom VBI Data */
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s->q_dma.bytesused -= buf->bytesused;
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ivtv_process_vbi_data(itv, buf, 0, s->type);
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s->q_dma.bytesused += buf->bytesused;
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list_for_each(p, &s->q_dma.list) {
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buf = list_entry(p, struct ivtv_buffer, list);
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/* Parse and Groom VBI Data */
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s->q_dma.bytesused -= buf->bytesused;
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ivtv_process_vbi_data(itv, buf, 0, s->type);
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s->q_dma.bytesused += buf->bytesused;
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}
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if (s->id == -1) {
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ivtv_queue_move(s, &s->q_dma, NULL, &s->q_free, 0);
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return;
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@ -351,10 +368,14 @@ static void ivtv_dma_enc_start(struct ivtv_stream *s)
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struct ivtv_stream *s_vbi = &itv->streams[IVTV_ENC_STREAM_TYPE_VBI];
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int i;
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IVTV_DEBUG_DMA("start %s for %s\n", ivtv_use_dma(s) ? "DMA" : "PIO", s->name);
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if (s->q_predma.bytesused)
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ivtv_queue_move(s, &s->q_predma, NULL, &s->q_dma, s->q_predma.bytesused);
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IVTV_DEBUG_DMA("start DMA for %s\n", s->name);
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s->SGarray[s->SG_length - 1].size = cpu_to_le32(le32_to_cpu(s->SGarray[s->SG_length - 1].size) + 256);
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if (ivtv_use_dma(s))
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s->SGarray[s->SG_length - 1].size =
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cpu_to_le32(le32_to_cpu(s->SGarray[s->SG_length - 1].size) + 256);
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/* If this is an MPEG stream, and VBI data is also pending, then append the
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VBI DMA to the MPEG DMA and transfer both sets of data at once.
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@ -368,7 +389,8 @@ static void ivtv_dma_enc_start(struct ivtv_stream *s)
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if (s->type == IVTV_ENC_STREAM_TYPE_MPG && s_vbi->SG_length &&
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s->SG_length + s_vbi->SG_length <= s->buffers) {
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ivtv_queue_move(s_vbi, &s_vbi->q_predma, NULL, &s_vbi->q_dma, s_vbi->q_predma.bytesused);
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s_vbi->SGarray[s_vbi->SG_length - 1].size = cpu_to_le32(le32_to_cpu(s_vbi->SGarray[s->SG_length - 1].size) + 256);
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if (ivtv_use_dma(s_vbi))
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s_vbi->SGarray[s_vbi->SG_length - 1].size = cpu_to_le32(le32_to_cpu(s_vbi->SGarray[s->SG_length - 1].size) + 256);
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for (i = 0; i < s_vbi->SG_length; i++) {
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s->SGarray[s->SG_length++] = s_vbi->SGarray[i];
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}
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@ -381,14 +403,26 @@ static void ivtv_dma_enc_start(struct ivtv_stream *s)
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/* Mark last buffer size for Interrupt flag */
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s->SGarray[s->SG_length - 1].size |= cpu_to_le32(0x80000000);
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/* Sync Hardware SG List of buffers */
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ivtv_stream_sync_for_device(s);
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write_reg(s->SG_handle, IVTV_REG_ENCDMAADDR);
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write_reg_sync(read_reg(IVTV_REG_DMAXFER) | 0x02, IVTV_REG_DMAXFER);
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set_bit(IVTV_F_I_DMA, &itv->i_flags);
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itv->cur_dma_stream = s->type;
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itv->dma_timer.expires = jiffies + HZ / 10;
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add_timer(&itv->dma_timer);
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if (ivtv_use_pio(s)) {
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for (i = 0; i < s->SG_length; i++) {
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s->PIOarray[i].src = le32_to_cpu(s->SGarray[i].src);
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s->PIOarray[i].size = le32_to_cpu(s->SGarray[i].size);
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}
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set_bit(IVTV_F_I_WORK_HANDLER_PIO, &itv->i_flags);
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set_bit(IVTV_F_I_HAVE_WORK, &itv->i_flags);
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set_bit(IVTV_F_I_PIO, &itv->i_flags);
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itv->cur_pio_stream = s->type;
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}
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else {
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/* Sync Hardware SG List of buffers */
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ivtv_stream_sync_for_device(s);
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write_reg(s->SG_handle, IVTV_REG_ENCDMAADDR);
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write_reg_sync(read_reg(IVTV_REG_DMAXFER) | 0x02, IVTV_REG_DMAXFER);
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set_bit(IVTV_F_I_DMA, &itv->i_flags);
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itv->cur_dma_stream = s->type;
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itv->dma_timer.expires = jiffies + HZ / 10;
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add_timer(&itv->dma_timer);
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}
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}
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static void ivtv_dma_dec_start(struct ivtv_stream *s)
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@ -489,6 +523,40 @@ static void ivtv_irq_enc_dma_complete(struct ivtv *itv)
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wake_up(&itv->dma_waitq);
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}
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static void ivtv_irq_enc_pio_complete(struct ivtv *itv)
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{
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struct ivtv_stream *s;
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if (itv->cur_pio_stream < 0 || itv->cur_pio_stream >= IVTV_MAX_STREAMS) {
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itv->cur_pio_stream = -1;
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return;
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}
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s = &itv->streams[itv->cur_pio_stream];
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IVTV_DEBUG_IRQ("ENC PIO COMPLETE %s\n", s->name);
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s->SG_length = 0;
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clear_bit(IVTV_F_I_ENC_VBI, &itv->i_flags);
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clear_bit(IVTV_F_I_PIO, &itv->i_flags);
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itv->cur_pio_stream = -1;
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dma_post(s);
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if (s->type == IVTV_ENC_STREAM_TYPE_MPG)
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ivtv_vapi(itv, CX2341X_ENC_SCHED_DMA_TO_HOST, 3, 0, 0, 0);
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else if (s->type == IVTV_ENC_STREAM_TYPE_YUV)
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ivtv_vapi(itv, CX2341X_ENC_SCHED_DMA_TO_HOST, 3, 0, 0, 1);
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else if (s->type == IVTV_ENC_STREAM_TYPE_PCM)
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ivtv_vapi(itv, CX2341X_ENC_SCHED_DMA_TO_HOST, 3, 0, 0, 2);
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clear_bit(IVTV_F_I_PIO, &itv->i_flags);
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if (test_and_clear_bit(IVTV_F_S_DMA_HAS_VBI, &s->s_flags)) {
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u32 tmp;
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s = &itv->streams[IVTV_ENC_STREAM_TYPE_VBI];
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tmp = s->dma_offset;
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s->dma_offset = itv->vbi.dma_offset;
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dma_post(s);
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s->dma_offset = tmp;
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}
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wake_up(&itv->dma_waitq);
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}
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static void ivtv_irq_dma_err(struct ivtv *itv)
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{
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u32 data[CX2341X_MBOX_MAX_DATA];
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@ -532,13 +600,7 @@ static void ivtv_irq_enc_start_cap(struct ivtv *itv)
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clear_bit(IVTV_F_I_ENC_VBI, &itv->i_flags);
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s = &itv->streams[ivtv_stream_map[data[0]]];
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if (!stream_enc_dma_append(s, data)) {
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if (ivtv_use_pio(s)) {
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dma_post(s);
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ivtv_vapi(itv, CX2341X_ENC_SCHED_DMA_TO_HOST, 3, 0, 0, data[0]);
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}
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else {
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set_bit(IVTV_F_S_DMA_PENDING, &s->s_flags);
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}
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set_bit(ivtv_use_pio(s) ? IVTV_F_S_PIO_PENDING : IVTV_F_S_DMA_PENDING, &s->s_flags);
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}
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}
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@ -551,15 +613,6 @@ static void ivtv_irq_enc_vbi_cap(struct ivtv *itv)
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IVTV_DEBUG_IRQ("ENC START VBI CAP\n");
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s = &itv->streams[IVTV_ENC_STREAM_TYPE_VBI];
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if (ivtv_use_pio(s)) {
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if (stream_enc_dma_append(s, data))
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return;
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if (s->q_predma.bytesused)
|
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ivtv_queue_move(s, &s->q_predma, NULL, &s->q_dma, s->q_predma.bytesused);
|
||||
s->SG_length = 0;
|
||||
dma_post(s);
|
||||
return;
|
||||
}
|
||||
/* If more than two VBI buffers are pending, then
|
||||
clear the old ones and start with this new one.
|
||||
This can happen during transition stages when MPEG capturing is
|
||||
|
|
@ -582,11 +635,11 @@ static void ivtv_irq_enc_vbi_cap(struct ivtv *itv)
|
|||
if (!stream_enc_dma_append(s, data) &&
|
||||
!test_bit(IVTV_F_S_STREAMING, &s_mpg->s_flags)) {
|
||||
set_bit(IVTV_F_I_ENC_VBI, &itv->i_flags);
|
||||
set_bit(IVTV_F_S_DMA_PENDING, &s->s_flags);
|
||||
set_bit(ivtv_use_pio(s) ? IVTV_F_S_PIO_PENDING : IVTV_F_S_DMA_PENDING, &s->s_flags);
|
||||
}
|
||||
}
|
||||
|
||||
static void ivtv_irq_dev_vbi_reinsert(struct ivtv *itv)
|
||||
static void ivtv_irq_dec_vbi_reinsert(struct ivtv *itv)
|
||||
{
|
||||
u32 data[CX2341X_MBOX_MAX_DATA];
|
||||
struct ivtv_stream *s = &itv->streams[IVTV_DEC_STREAM_TYPE_VBI];
|
||||
|
|
@ -594,7 +647,7 @@ static void ivtv_irq_dev_vbi_reinsert(struct ivtv *itv)
|
|||
IVTV_DEBUG_IRQ("DEC VBI REINSERT\n");
|
||||
if (test_bit(IVTV_F_S_CLAIMED, &s->s_flags) &&
|
||||
!stream_enc_dma_append(s, data)) {
|
||||
dma_post(s);
|
||||
set_bit(IVTV_F_S_PIO_PENDING, &s->s_flags);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -657,7 +710,6 @@ static void ivtv_irq_vsync(struct ivtv *itv)
|
|||
}
|
||||
if (frame != (itv->lastVsyncFrame & 1)) {
|
||||
struct ivtv_stream *s = ivtv_get_output_stream(itv);
|
||||
int work = 0;
|
||||
|
||||
itv->lastVsyncFrame += 1;
|
||||
if (frame == 0) {
|
||||
|
|
@ -678,7 +730,7 @@ static void ivtv_irq_vsync(struct ivtv *itv)
|
|||
/* Send VBI to saa7127 */
|
||||
if (frame) {
|
||||
set_bit(IVTV_F_I_WORK_HANDLER_VBI, &itv->i_flags);
|
||||
work = 1;
|
||||
set_bit(IVTV_F_I_HAVE_WORK, &itv->i_flags);
|
||||
}
|
||||
|
||||
/* Check if we need to update the yuv registers */
|
||||
|
|
@ -691,11 +743,9 @@ static void ivtv_irq_vsync(struct ivtv *itv)
|
|||
itv->yuv_info.new_frame_info[last_dma_frame].update = 0;
|
||||
itv->yuv_info.yuv_forced_update = 0;
|
||||
set_bit(IVTV_F_I_WORK_HANDLER_YUV, &itv->i_flags);
|
||||
work = 1;
|
||||
set_bit(IVTV_F_I_HAVE_WORK, &itv->i_flags);
|
||||
}
|
||||
}
|
||||
if (work)
|
||||
queue_work(itv->irq_work_queues, &itv->irq_work_queue);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -755,6 +805,10 @@ irqreturn_t ivtv_irq_handler(int irq, void *dev_id)
|
|||
ivtv_irq_enc_dma_complete(itv);
|
||||
}
|
||||
|
||||
if (combo & IVTV_IRQ_ENC_PIO_COMPLETE) {
|
||||
ivtv_irq_enc_pio_complete(itv);
|
||||
}
|
||||
|
||||
if (combo & IVTV_IRQ_DMA_ERR) {
|
||||
ivtv_irq_dma_err(itv);
|
||||
}
|
||||
|
|
@ -768,7 +822,7 @@ irqreturn_t ivtv_irq_handler(int irq, void *dev_id)
|
|||
}
|
||||
|
||||
if (combo & IVTV_IRQ_DEC_VBI_RE_INSERT) {
|
||||
ivtv_irq_dev_vbi_reinsert(itv);
|
||||
ivtv_irq_dec_vbi_reinsert(itv);
|
||||
}
|
||||
|
||||
if (combo & IVTV_IRQ_ENC_EOS) {
|
||||
|
|
@ -813,6 +867,22 @@ irqreturn_t ivtv_irq_handler(int irq, void *dev_id)
|
|||
}
|
||||
}
|
||||
|
||||
if ((combo & IVTV_IRQ_DMA) && !test_bit(IVTV_F_I_PIO, &itv->i_flags)) {
|
||||
for (i = 0; i < IVTV_MAX_STREAMS; i++) {
|
||||
int idx = (i + itv->irq_rr_idx++) % IVTV_MAX_STREAMS;
|
||||
struct ivtv_stream *s = &itv->streams[idx];
|
||||
|
||||
if (!test_and_clear_bit(IVTV_F_S_PIO_PENDING, &s->s_flags))
|
||||
continue;
|
||||
if (s->type == IVTV_DEC_STREAM_TYPE_VBI || s->type < IVTV_DEC_STREAM_TYPE_MPG)
|
||||
ivtv_dma_enc_start(s);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (test_and_clear_bit(IVTV_F_I_HAVE_WORK, &itv->i_flags))
|
||||
queue_work(itv->irq_work_queues, &itv->irq_work_queue);
|
||||
|
||||
spin_unlock(&itv->dma_reg_lock);
|
||||
|
||||
/* If we've just handled a 'forced' vsync, it's safest to say it
|
||||
|
|
|
|||
|
|
@ -195,14 +195,26 @@ int ivtv_stream_alloc(struct ivtv_stream *s)
|
|||
s->dma != PCI_DMA_NONE ? "DMA " : "",
|
||||
s->name, s->buffers, s->buf_size, s->buffers * s->buf_size / 1024);
|
||||
|
||||
/* Allocate DMA SG Arrays */
|
||||
if (s->dma != PCI_DMA_NONE) {
|
||||
s->SGarray = (struct ivtv_SG_element *)kzalloc(SGsize, GFP_KERNEL);
|
||||
if (s->SGarray == NULL) {
|
||||
IVTV_ERR("Could not allocate SGarray for %s stream\n", s->name);
|
||||
if (ivtv_might_use_pio(s)) {
|
||||
s->PIOarray = (struct ivtv_SG_element *)kzalloc(SGsize, GFP_KERNEL);
|
||||
if (s->PIOarray == NULL) {
|
||||
IVTV_ERR("Could not allocate PIOarray for %s stream\n", s->name);
|
||||
return -ENOMEM;
|
||||
}
|
||||
s->SG_length = 0;
|
||||
}
|
||||
|
||||
/* Allocate DMA SG Arrays */
|
||||
s->SGarray = (struct ivtv_SG_element *)kzalloc(SGsize, GFP_KERNEL);
|
||||
if (s->SGarray == NULL) {
|
||||
IVTV_ERR("Could not allocate SGarray for %s stream\n", s->name);
|
||||
if (ivtv_might_use_pio(s)) {
|
||||
kfree(s->PIOarray);
|
||||
s->PIOarray = NULL;
|
||||
}
|
||||
return -ENOMEM;
|
||||
}
|
||||
s->SG_length = 0;
|
||||
if (ivtv_might_use_dma(s)) {
|
||||
s->SG_handle = pci_map_single(itv->dev, s->SGarray, SGsize, s->dma);
|
||||
ivtv_stream_sync_for_cpu(s);
|
||||
}
|
||||
|
|
@ -219,7 +231,7 @@ int ivtv_stream_alloc(struct ivtv_stream *s)
|
|||
break;
|
||||
}
|
||||
INIT_LIST_HEAD(&buf->list);
|
||||
if (s->dma != PCI_DMA_NONE) {
|
||||
if (ivtv_might_use_dma(s)) {
|
||||
buf->dma_handle = pci_map_single(s->itv->dev,
|
||||
buf->buf, s->buf_size + 256, s->dma);
|
||||
ivtv_buf_sync_for_cpu(s, buf);
|
||||
|
|
@ -242,7 +254,7 @@ void ivtv_stream_free(struct ivtv_stream *s)
|
|||
|
||||
/* empty q_free */
|
||||
while ((buf = ivtv_dequeue(s, &s->q_free))) {
|
||||
if (s->dma != PCI_DMA_NONE)
|
||||
if (ivtv_might_use_dma(s))
|
||||
pci_unmap_single(s->itv->dev, buf->dma_handle,
|
||||
s->buf_size + 256, s->dma);
|
||||
kfree(buf->buf);
|
||||
|
|
@ -256,6 +268,9 @@ void ivtv_stream_free(struct ivtv_stream *s)
|
|||
sizeof(struct ivtv_SG_element) * s->buffers, PCI_DMA_TODEVICE);
|
||||
s->SG_handle = IVTV_DMA_UNMAPPED;
|
||||
}
|
||||
kfree(s->SGarray);
|
||||
kfree(s->PIOarray);
|
||||
s->PIOarray = NULL;
|
||||
s->SGarray = NULL;
|
||||
s->SG_length = 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -20,18 +20,43 @@
|
|||
*/
|
||||
|
||||
#define IVTV_DMA_UNMAPPED ((u32) -1)
|
||||
#define SLICED_VBI_PIO 1
|
||||
|
||||
/* ivtv_buffer utility functions */
|
||||
|
||||
static inline int ivtv_might_use_pio(struct ivtv_stream *s)
|
||||
{
|
||||
return s->dma == PCI_DMA_NONE || (SLICED_VBI_PIO && s->type == IVTV_ENC_STREAM_TYPE_VBI);
|
||||
}
|
||||
|
||||
static inline int ivtv_use_pio(struct ivtv_stream *s)
|
||||
{
|
||||
struct ivtv *itv = s->itv;
|
||||
|
||||
return s->dma == PCI_DMA_NONE ||
|
||||
(SLICED_VBI_PIO && s->type == IVTV_ENC_STREAM_TYPE_VBI && itv->vbi.sliced_in->service_set);
|
||||
}
|
||||
|
||||
static inline int ivtv_might_use_dma(struct ivtv_stream *s)
|
||||
{
|
||||
return s->dma != PCI_DMA_NONE;
|
||||
}
|
||||
|
||||
static inline int ivtv_use_dma(struct ivtv_stream *s)
|
||||
{
|
||||
return !ivtv_use_pio(s);
|
||||
}
|
||||
|
||||
static inline void ivtv_buf_sync_for_cpu(struct ivtv_stream *s, struct ivtv_buffer *buf)
|
||||
{
|
||||
if (s->dma != PCI_DMA_NONE)
|
||||
if (ivtv_use_dma(s))
|
||||
pci_dma_sync_single_for_cpu(s->itv->dev, buf->dma_handle,
|
||||
s->buf_size + 256, s->dma);
|
||||
}
|
||||
|
||||
static inline void ivtv_buf_sync_for_device(struct ivtv_stream *s, struct ivtv_buffer *buf)
|
||||
{
|
||||
if (s->dma != PCI_DMA_NONE)
|
||||
if (ivtv_use_dma(s))
|
||||
pci_dma_sync_single_for_device(s->itv->dev, buf->dma_handle,
|
||||
s->buf_size + 256, s->dma);
|
||||
}
|
||||
|
|
@ -53,12 +78,14 @@ void ivtv_stream_free(struct ivtv_stream *s);
|
|||
|
||||
static inline void ivtv_stream_sync_for_cpu(struct ivtv_stream *s)
|
||||
{
|
||||
pci_dma_sync_single_for_cpu(s->itv->dev, s->SG_handle,
|
||||
sizeof(struct ivtv_SG_element) * s->buffers, PCI_DMA_TODEVICE);
|
||||
if (ivtv_use_dma(s))
|
||||
pci_dma_sync_single_for_cpu(s->itv->dev, s->SG_handle,
|
||||
sizeof(struct ivtv_SG_element) * s->buffers, PCI_DMA_TODEVICE);
|
||||
}
|
||||
|
||||
static inline void ivtv_stream_sync_for_device(struct ivtv_stream *s)
|
||||
{
|
||||
pci_dma_sync_single_for_device(s->itv->dev, s->SG_handle,
|
||||
sizeof(struct ivtv_SG_element) * s->buffers, PCI_DMA_TODEVICE);
|
||||
if (ivtv_use_dma(s))
|
||||
pci_dma_sync_single_for_device(s->itv->dev, s->SG_handle,
|
||||
sizeof(struct ivtv_SG_element) * s->buffers, PCI_DMA_TODEVICE);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -450,7 +450,7 @@ void ivtv_disable_vbi(struct ivtv *itv)
|
|||
}
|
||||
|
||||
|
||||
void vbi_work_handler(struct ivtv *itv)
|
||||
void ivtv_vbi_work_handler(struct ivtv *itv)
|
||||
{
|
||||
struct v4l2_sliced_vbi_data data;
|
||||
|
||||
|
|
|
|||
|
|
@ -23,4 +23,4 @@ void ivtv_process_vbi_data(struct ivtv *itv, struct ivtv_buffer *buf,
|
|||
int ivtv_used_line(struct ivtv *itv, int line, int field);
|
||||
void ivtv_disable_vbi(struct ivtv *itv);
|
||||
void ivtv_set_vbi(unsigned long arg);
|
||||
void vbi_work_handler(struct ivtv *itv);
|
||||
void ivtv_vbi_work_handler(struct ivtv *itv);
|
||||
|
|
|
|||
Loading…
Reference in a new issue