mirror of
https://github.com/adulau/aha.git
synced 2024-12-27 19:26:25 +00:00
clocksource: SuperH MTU2 Timer driver
This patch adds a MTU2 driver for the SuperH architecture. The MTU2 driver is a platform driver with early platform support to allow using a MTU2 channel as only clockevent during system bootup. Clocksource on sh2a is currently unsupported due to code generation issues with 64-bit math, so at this point only periodic clockevent support is in place. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Magnus Damm
Paul Mundt
parent
7563431107
commit
d5ed4c2e5c
4 changed files with 381 additions and 0 deletions
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@ -113,6 +113,9 @@ config SYS_SUPPORTS_PCI
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config SYS_SUPPORTS_CMT
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bool
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config SYS_SUPPORTS_MTU2
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bool
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config STACKTRACE_SUPPORT
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def_bool y
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@ -478,6 +481,14 @@ config SH_MTU2
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help
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This enables the use of the MTU2 as the system timer.
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config SH_TIMER_MTU2
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bool "MTU2 timer driver"
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depends on SYS_SUPPORTS_MTU2 && !SH_MTU2
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default y
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select GENERIC_CLOCKEVENTS
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help
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This enables build of the MTU2 timer driver.
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config SH_TIMER_IRQ
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int
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default "28" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 || \
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@ -3,3 +3,4 @@ obj-$(CONFIG_X86_CYCLONE_TIMER) += cyclone.o
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obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o
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obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o
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obj-$(CONFIG_SH_TIMER_CMT) += sh_cmt.o
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obj-$(CONFIG_SH_TIMER_MTU2) += sh_mtu2.o
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357
drivers/clocksource/sh_mtu2.c
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357
drivers/clocksource/sh_mtu2.c
Normal file
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@ -0,0 +1,357 @@
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/*
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* SuperH Timer Support - MTU2
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*
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* Copyright (C) 2009 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/irq.h>
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#include <linux/err.h>
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#include <linux/clockchips.h>
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#include <linux/sh_mtu2.h>
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struct sh_mtu2_priv {
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void __iomem *mapbase;
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struct clk *clk;
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struct irqaction irqaction;
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struct platform_device *pdev;
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unsigned long rate;
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unsigned long periodic;
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struct clock_event_device ced;
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};
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static DEFINE_SPINLOCK(sh_mtu2_lock);
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#define TSTR -1 /* shared register */
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#define TCR 0 /* channel register */
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#define TMDR 1 /* channel register */
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#define TIOR 2 /* channel register */
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#define TIER 3 /* channel register */
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#define TSR 4 /* channel register */
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#define TCNT 5 /* channel register */
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#define TGR 6 /* channel register */
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static unsigned long mtu2_reg_offs[] = {
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[TCR] = 0,
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[TMDR] = 1,
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[TIOR] = 2,
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[TIER] = 4,
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[TSR] = 5,
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[TCNT] = 6,
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[TGR] = 8,
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};
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static inline unsigned long sh_mtu2_read(struct sh_mtu2_priv *p, int reg_nr)
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{
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struct sh_mtu2_config *cfg = p->pdev->dev.platform_data;
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void __iomem *base = p->mapbase;
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unsigned long offs;
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if (reg_nr == TSTR)
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return ioread8(base + cfg->channel_offset);
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offs = mtu2_reg_offs[reg_nr];
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if ((reg_nr == TCNT) || (reg_nr == TGR))
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return ioread16(base + offs);
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else
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return ioread8(base + offs);
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}
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static inline void sh_mtu2_write(struct sh_mtu2_priv *p, int reg_nr,
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unsigned long value)
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{
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struct sh_mtu2_config *cfg = p->pdev->dev.platform_data;
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void __iomem *base = p->mapbase;
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unsigned long offs;
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if (reg_nr == TSTR) {
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iowrite8(value, base + cfg->channel_offset);
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return;
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}
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offs = mtu2_reg_offs[reg_nr];
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if ((reg_nr == TCNT) || (reg_nr == TGR))
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iowrite16(value, base + offs);
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else
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iowrite8(value, base + offs);
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}
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static void sh_mtu2_start_stop_ch(struct sh_mtu2_priv *p, int start)
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{
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struct sh_mtu2_config *cfg = p->pdev->dev.platform_data;
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unsigned long flags, value;
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/* start stop register shared by multiple timer channels */
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spin_lock_irqsave(&sh_mtu2_lock, flags);
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value = sh_mtu2_read(p, TSTR);
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if (start)
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value |= 1 << cfg->timer_bit;
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else
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value &= ~(1 << cfg->timer_bit);
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sh_mtu2_write(p, TSTR, value);
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spin_unlock_irqrestore(&sh_mtu2_lock, flags);
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}
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static int sh_mtu2_enable(struct sh_mtu2_priv *p)
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{
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struct sh_mtu2_config *cfg = p->pdev->dev.platform_data;
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int ret;
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/* enable clock */
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ret = clk_enable(p->clk);
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if (ret) {
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pr_err("sh_mtu2: cannot enable clock \"%s\"\n", cfg->clk);
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return ret;
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}
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/* make sure channel is disabled */
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sh_mtu2_start_stop_ch(p, 0);
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p->rate = clk_get_rate(p->clk) / 64;
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p->periodic = (p->rate + HZ/2) / HZ;
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/* "Periodic Counter Operation" */
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sh_mtu2_write(p, TCR, 0x23); /* TGRA clear, divide clock by 64 */
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sh_mtu2_write(p, TIOR, 0);
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sh_mtu2_write(p, TGR, p->periodic);
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sh_mtu2_write(p, TCNT, 0);
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sh_mtu2_write(p, TMDR, 0);
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sh_mtu2_write(p, TIER, 0x01);
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/* enable channel */
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sh_mtu2_start_stop_ch(p, 1);
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return 0;
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}
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static void sh_mtu2_disable(struct sh_mtu2_priv *p)
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{
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/* disable channel */
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sh_mtu2_start_stop_ch(p, 0);
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/* stop clock */
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clk_disable(p->clk);
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}
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static irqreturn_t sh_mtu2_interrupt(int irq, void *dev_id)
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{
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struct sh_mtu2_priv *p = dev_id;
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/* acknowledge interrupt */
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sh_mtu2_read(p, TSR);
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sh_mtu2_write(p, TSR, 0xfe);
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/* notify clockevent layer */
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p->ced.event_handler(&p->ced);
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return IRQ_HANDLED;
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}
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static struct sh_mtu2_priv *ced_to_sh_mtu2(struct clock_event_device *ced)
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{
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return container_of(ced, struct sh_mtu2_priv, ced);
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}
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static void sh_mtu2_clock_event_mode(enum clock_event_mode mode,
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struct clock_event_device *ced)
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{
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struct sh_mtu2_priv *p = ced_to_sh_mtu2(ced);
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int disabled = 0;
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/* deal with old setting first */
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switch (ced->mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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sh_mtu2_disable(p);
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disabled = 1;
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break;
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default:
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break;
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}
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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pr_info("sh_mtu2: %s used for periodic clock events\n",
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ced->name);
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sh_mtu2_enable(p);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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if (!disabled)
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sh_mtu2_disable(p);
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break;
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case CLOCK_EVT_MODE_SHUTDOWN:
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default:
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break;
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}
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}
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static void sh_mtu2_register_clockevent(struct sh_mtu2_priv *p,
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char *name, unsigned long rating)
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{
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struct clock_event_device *ced = &p->ced;
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int ret;
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memset(ced, 0, sizeof(*ced));
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ced->name = name;
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ced->features = CLOCK_EVT_FEAT_PERIODIC;
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ced->rating = rating;
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ced->cpumask = cpumask_of(0);
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ced->set_mode = sh_mtu2_clock_event_mode;
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ret = setup_irq(p->irqaction.irq, &p->irqaction);
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if (ret) {
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pr_err("sh_mtu2: failed to request irq %d\n",
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p->irqaction.irq);
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return;
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}
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pr_info("sh_mtu2: %s used for clock events\n", ced->name);
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clockevents_register_device(ced);
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}
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int sh_mtu2_register(struct sh_mtu2_priv *p, char *name,
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unsigned long clockevent_rating)
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{
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if (clockevent_rating)
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sh_mtu2_register_clockevent(p, name, clockevent_rating);
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return 0;
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}
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static int sh_mtu2_setup(struct sh_mtu2_priv *p, struct platform_device *pdev)
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{
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struct sh_mtu2_config *cfg = pdev->dev.platform_data;
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struct resource *res;
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int irq, ret;
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ret = -ENXIO;
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memset(p, 0, sizeof(*p));
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p->pdev = pdev;
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if (!cfg) {
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dev_err(&p->pdev->dev, "missing platform data\n");
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goto err0;
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}
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platform_set_drvdata(pdev, p);
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res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(&p->pdev->dev, "failed to get I/O memory\n");
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goto err0;
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}
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irq = platform_get_irq(p->pdev, 0);
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if (irq < 0) {
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dev_err(&p->pdev->dev, "failed to get irq\n");
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goto err0;
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}
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/* map memory, let mapbase point to our channel */
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p->mapbase = ioremap_nocache(res->start, resource_size(res));
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if (p->mapbase == NULL) {
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pr_err("sh_mtu2: failed to remap I/O memory\n");
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goto err0;
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}
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/* setup data for setup_irq() (too early for request_irq()) */
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p->irqaction.name = cfg->name;
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p->irqaction.handler = sh_mtu2_interrupt;
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p->irqaction.dev_id = p;
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p->irqaction.irq = irq;
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p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL;
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p->irqaction.mask = CPU_MASK_NONE;
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/* get hold of clock */
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p->clk = clk_get(&p->pdev->dev, cfg->clk);
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if (IS_ERR(p->clk)) {
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pr_err("sh_mtu2: cannot get clock \"%s\"\n", cfg->clk);
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ret = PTR_ERR(p->clk);
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goto err1;
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}
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return sh_mtu2_register(p, cfg->name, cfg->clockevent_rating);
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err1:
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iounmap(p->mapbase);
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err0:
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return ret;
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}
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static int __devinit sh_mtu2_probe(struct platform_device *pdev)
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{
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struct sh_mtu2_priv *p = platform_get_drvdata(pdev);
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struct sh_mtu2_config *cfg = pdev->dev.platform_data;
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int ret;
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if (p) {
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pr_info("sh_mtu2: %s kept as earlytimer\n", cfg->name);
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return 0;
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}
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p = kmalloc(sizeof(*p), GFP_KERNEL);
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if (p == NULL) {
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dev_err(&pdev->dev, "failed to allocate driver data\n");
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return -ENOMEM;
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}
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ret = sh_mtu2_setup(p, pdev);
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if (ret) {
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kfree(p);
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platform_set_drvdata(pdev, NULL);
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}
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return ret;
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}
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static int __devexit sh_mtu2_remove(struct platform_device *pdev)
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{
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return -EBUSY; /* cannot unregister clockevent */
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}
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static struct platform_driver sh_mtu2_device_driver = {
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.probe = sh_mtu2_probe,
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.remove = __devexit_p(sh_mtu2_remove),
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.driver = {
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.name = "sh_mtu2",
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}
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};
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static int __init sh_mtu2_init(void)
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{
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return platform_driver_register(&sh_mtu2_device_driver);
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}
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static void __exit sh_mtu2_exit(void)
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{
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platform_driver_unregister(&sh_mtu2_device_driver);
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}
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early_platform_init("earlytimer", &sh_mtu2_device_driver);
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module_init(sh_mtu2_init);
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module_exit(sh_mtu2_exit);
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MODULE_AUTHOR("Magnus Damm");
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MODULE_DESCRIPTION("SuperH MTU2 Timer Driver");
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MODULE_LICENSE("GPL v2");
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12
include/linux/sh_mtu2.h
Normal file
12
include/linux/sh_mtu2.h
Normal file
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@ -0,0 +1,12 @@
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#ifndef __SH_MTU2_H__
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#define __SH_MTU2_H__
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struct sh_mtu2_config {
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char *name;
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int channel_offset;
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int timer_bit;
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char *clk;
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unsigned long clockevent_rating;
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};
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#endif /* __SH_MTU2_H__ */
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