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[ARM] omap: handle RATE_CKCTL via .set_rate/.round_rate methods
It makes no sense to have the CKCTL rate selection implemented as a flag and a special exception in the top level set_rate/round_rate methods. Provide CKCTL set_rate/round_rate methods, and use these for where ever RATE_CKCTL is used and they're not already overridden. This allows us to remove the RATE_CKCTL flag. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
parent
9a5fedac18
commit
d5e6072b75
3 changed files with 70 additions and 62 deletions
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@ -216,9 +216,6 @@ static int calc_dsor_exp(struct clk *clk, unsigned long rate)
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struct clk * parent;
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unsigned dsor_exp;
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if (unlikely(!(clk->flags & RATE_CKCTL)))
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return -EINVAL;
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parent = clk->parent;
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if (unlikely(parent == NULL))
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return -EIO;
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@ -307,26 +304,52 @@ static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
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static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
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{
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int ret = -EINVAL;
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int dsor_exp;
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__u16 regval;
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int dsor_exp;
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u16 regval;
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if (clk->flags & RATE_CKCTL) {
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dsor_exp = calc_dsor_exp(clk, rate);
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if (dsor_exp > 3)
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dsor_exp = -EINVAL;
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if (dsor_exp < 0)
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return dsor_exp;
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dsor_exp = calc_dsor_exp(clk, rate);
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if (dsor_exp > 3)
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dsor_exp = -EINVAL;
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if (dsor_exp < 0)
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return dsor_exp;
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regval = __raw_readw(DSP_CKCTL);
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regval &= ~(3 << clk->rate_offset);
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regval |= dsor_exp << clk->rate_offset;
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__raw_writew(regval, DSP_CKCTL);
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clk->rate = clk->parent->rate / (1 << dsor_exp);
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ret = 0;
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}
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regval = __raw_readw(DSP_CKCTL);
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regval &= ~(3 << clk->rate_offset);
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regval |= dsor_exp << clk->rate_offset;
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__raw_writew(regval, DSP_CKCTL);
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clk->rate = clk->parent->rate / (1 << dsor_exp);
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return ret;
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return 0;
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}
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static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate)
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{
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int dsor_exp = calc_dsor_exp(clk, rate);
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if (dsor_exp < 0)
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return dsor_exp;
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if (dsor_exp > 3)
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dsor_exp = 3;
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return clk->parent->rate / (1 << dsor_exp);
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}
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static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate)
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{
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int dsor_exp;
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u16 regval;
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dsor_exp = calc_dsor_exp(clk, rate);
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if (dsor_exp > 3)
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dsor_exp = -EINVAL;
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if (dsor_exp < 0)
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return dsor_exp;
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regval = omap_readw(ARM_CKCTL);
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regval &= ~(3 << clk->rate_offset);
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regval |= dsor_exp << clk->rate_offset;
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regval = verify_ckctl_value(regval);
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omap_writew(regval, ARM_CKCTL);
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clk->rate = clk->parent->rate / (1 << dsor_exp);
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return 0;
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}
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static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate)
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@ -572,20 +595,9 @@ static const struct clkops clkops_generic = {
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static long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
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{
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int dsor_exp;
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if (clk->flags & RATE_FIXED)
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return clk->rate;
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if (clk->flags & RATE_CKCTL) {
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dsor_exp = calc_dsor_exp(clk, rate);
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if (dsor_exp < 0)
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return dsor_exp;
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if (dsor_exp > 3)
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dsor_exp = 3;
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return clk->parent->rate / (1 << dsor_exp);
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}
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if (clk->round_rate != NULL)
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return clk->round_rate(clk, rate);
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@ -595,27 +607,9 @@ static long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
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static int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
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{
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int ret = -EINVAL;
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int dsor_exp;
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__u16 regval;
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if (clk->set_rate)
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ret = clk->set_rate(clk, rate);
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else if (clk->flags & RATE_CKCTL) {
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dsor_exp = calc_dsor_exp(clk, rate);
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if (dsor_exp > 3)
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dsor_exp = -EINVAL;
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if (dsor_exp < 0)
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return dsor_exp;
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regval = omap_readw(ARM_CKCTL);
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regval &= ~(3 << clk->rate_offset);
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regval |= dsor_exp << clk->rate_offset;
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regval = verify_ckctl_value(regval);
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omap_writew(regval, ARM_CKCTL);
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clk->rate = clk->parent->rate / (1 << dsor_exp);
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ret = 0;
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}
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return ret;
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}
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@ -27,6 +27,9 @@ static void omap1_init_ext_clk(struct clk * clk);
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static int omap1_select_table_rate(struct clk * clk, unsigned long rate);
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static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate);
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static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate);
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static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate);
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struct mpu_rate {
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unsigned long rate;
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unsigned long xtal;
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@ -189,9 +192,11 @@ static struct clk arm_ck = {
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.ops = &clkops_null,
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.parent = &ck_dpll1,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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CLOCK_IN_OMAP310 | RATE_CKCTL | RATE_PROPAGATES,
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CLOCK_IN_OMAP310 | RATE_PROPAGATES,
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.rate_offset = CKCTL_ARMDIV_OFFSET,
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.recalc = &omap1_ckctl_recalc,
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.round_rate = omap1_clk_round_rate_ckctl_arm,
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.set_rate = omap1_clk_set_rate_ckctl_arm,
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};
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static struct arm_idlect1_clk armper_ck = {
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@ -200,12 +205,13 @@ static struct arm_idlect1_clk armper_ck = {
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.ops = &clkops_generic,
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.parent = &ck_dpll1,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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CLOCK_IN_OMAP310 | RATE_CKCTL |
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CLOCK_IDLE_CONTROL,
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CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
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.enable_reg = (void __iomem *)ARM_IDLECT2,
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.enable_bit = EN_PERCK,
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.rate_offset = CKCTL_PERDIV_OFFSET,
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.recalc = &omap1_ckctl_recalc,
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.round_rate = omap1_clk_round_rate_ckctl_arm,
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.set_rate = omap1_clk_set_rate_ckctl_arm,
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},
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.idlect_shift = 2,
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};
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@ -279,22 +285,24 @@ static struct clk dsp_ck = {
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.name = "dsp_ck",
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.ops = &clkops_generic,
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.parent = &ck_dpll1,
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.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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RATE_CKCTL,
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.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
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.enable_reg = (void __iomem *)ARM_CKCTL,
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.enable_bit = EN_DSPCK,
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.rate_offset = CKCTL_DSPDIV_OFFSET,
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.recalc = &omap1_ckctl_recalc,
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.round_rate = omap1_clk_round_rate_ckctl_arm,
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.set_rate = omap1_clk_set_rate_ckctl_arm,
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};
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static struct clk dspmmu_ck = {
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.name = "dspmmu_ck",
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.ops = &clkops_null,
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.parent = &ck_dpll1,
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.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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RATE_CKCTL,
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.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
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.rate_offset = CKCTL_DSPMMUDIV_OFFSET,
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.recalc = &omap1_ckctl_recalc,
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.round_rate = omap1_clk_round_rate_ckctl_arm,
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.set_rate = omap1_clk_set_rate_ckctl_arm,
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};
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static struct clk dspper_ck = {
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@ -302,11 +310,12 @@ static struct clk dspper_ck = {
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.ops = &clkops_dspck,
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.parent = &ck_dpll1,
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.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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RATE_CKCTL | VIRTUAL_IO_ADDRESS,
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VIRTUAL_IO_ADDRESS,
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.enable_reg = DSP_IDLECT2,
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.enable_bit = EN_PERCK,
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.rate_offset = CKCTL_PERDIV_OFFSET,
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.recalc = &omap1_ckctl_recalc_dsp_domain,
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.round_rate = omap1_clk_round_rate_ckctl_arm,
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.set_rate = &omap1_clk_set_rate_dsp_domain,
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};
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@ -340,10 +349,11 @@ static struct arm_idlect1_clk tc_ck = {
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.parent = &ck_dpll1,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 |
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RATE_CKCTL | RATE_PROPAGATES |
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CLOCK_IDLE_CONTROL,
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RATE_PROPAGATES | CLOCK_IDLE_CONTROL,
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.rate_offset = CKCTL_TCDIV_OFFSET,
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.recalc = &omap1_ckctl_recalc,
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.round_rate = omap1_clk_round_rate_ckctl_arm,
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.set_rate = omap1_clk_set_rate_ckctl_arm,
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},
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.idlect_shift = 6,
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};
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@ -466,11 +476,13 @@ static struct clk lcd_ck_16xx = {
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.name = "lcd_ck",
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.ops = &clkops_generic,
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.parent = &ck_dpll1,
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.flags = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 | RATE_CKCTL,
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.flags = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730,
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.enable_reg = (void __iomem *)ARM_IDLECT2,
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.enable_bit = EN_LCDCK,
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.rate_offset = CKCTL_LCDDIV_OFFSET,
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.recalc = &omap1_ckctl_recalc,
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.round_rate = omap1_clk_round_rate_ckctl_arm,
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.set_rate = omap1_clk_set_rate_ckctl_arm,
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};
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static struct arm_idlect1_clk lcd_ck_1510 = {
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@ -479,11 +491,13 @@ static struct arm_idlect1_clk lcd_ck_1510 = {
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.ops = &clkops_generic,
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.parent = &ck_dpll1,
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.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
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RATE_CKCTL | CLOCK_IDLE_CONTROL,
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CLOCK_IDLE_CONTROL,
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.enable_reg = (void __iomem *)ARM_IDLECT2,
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.enable_bit = EN_LCDCK,
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.rate_offset = CKCTL_LCDDIV_OFFSET,
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.recalc = &omap1_ckctl_recalc,
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.round_rate = omap1_clk_round_rate_ckctl_arm,
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.set_rate = omap1_clk_set_rate_ckctl_arm,
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},
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.idlect_shift = 3,
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};
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@ -124,7 +124,7 @@ extern void clk_enable_init_clocks(void);
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extern const struct clkops clkops_null;
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/* Clock flags */
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#define RATE_CKCTL (1 << 0) /* Main fixed ratio clocks */
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/* bit 0 is free */
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#define RATE_FIXED (1 << 1) /* Fixed clock rate */
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#define RATE_PROPAGATES (1 << 2) /* Program children too */
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/* bits 3-4 are free */
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