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[PATCH] ioc4: PCI bus speed detection
Several hardware features of SGI's IOC4 I/O controller chip require timing-related driver calculations dependent upon the PCI bus speed. This patch enables the core IOC4 driver code to detect the actual bus speed and store a value that can later be used by the IOC4 subdrivers as needed. Signed-off-by: Brent Casavant <bcasavan@sgi.com> Acked-by: Pat Gefre <pfg@sgi.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Brent Casavant
Linus Torvalds
parent
e5d310b349
commit
d4c477ca54
4 changed files with 177 additions and 21 deletions
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@ -299,7 +299,6 @@ struct ioc4_serial {
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} ioc4_serial;
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/* UART clock speed */
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#define IOC4_SER_XIN_CLK IOC4_SER_XIN_CLK_66
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#define IOC4_SER_XIN_CLK_66 66666667
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#define IOC4_SER_XIN_CLK_33 33333333
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@ -1012,21 +1011,20 @@ static irqreturn_t ioc4_intr(int irq, void *arg, struct pt_regs *regs)
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* ioc4_attach_local - Device initialization.
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* Called at *_attach() time for each
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* IOC4 with serial ports in the system.
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* @control: ioc4_control ptr
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* @pdev: PCI handle for this device
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* @soft: soft struct for this device
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* @ioc4: ioc4 mem space
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* @idd: Master module data for this IOC4
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*/
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static int inline ioc4_attach_local(struct pci_dev *pdev,
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struct ioc4_control *control,
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struct ioc4_soft *soft, void __iomem *ioc4_misc,
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void __iomem *ioc4_serial)
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static int inline ioc4_attach_local(struct ioc4_driver_data *idd)
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{
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struct ioc4_port *port;
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struct ioc4_port *ports[IOC4_NUM_SERIAL_PORTS];
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int port_number;
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uint16_t ioc4_revid_min = 62;
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uint16_t ioc4_revid;
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struct pci_dev *pdev = idd->idd_pdev;
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struct ioc4_control* control = idd->idd_serial_data;
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struct ioc4_soft *soft = control->ic_soft;
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void __iomem *ioc4_misc = idd->idd_misc_regs;
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void __iomem *ioc4_serial = soft->is_ioc4_serial_addr;
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/* IOC4 firmware must be at least rev 62 */
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pci_read_config_word(pdev, PCI_COMMAND_SPECIAL, &ioc4_revid);
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@ -1063,7 +1061,15 @@ static int inline ioc4_attach_local(struct pci_dev *pdev,
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port->ip_ioc4_soft = soft;
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port->ip_pdev = pdev;
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port->ip_ienb = 0;
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port->ip_pci_bus_speed = IOC4_SER_XIN_CLK;
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/* Use baud rate calculations based on detected PCI
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* bus speed. Simply test whether the PCI clock is
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* running closer to 66MHz or 33MHz.
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*/
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if (idd->count_period/IOC4_EXTINT_COUNT_DIVISOR < 20) {
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port->ip_pci_bus_speed = IOC4_SER_XIN_CLK_66;
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} else {
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port->ip_pci_bus_speed = IOC4_SER_XIN_CLK_33;
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}
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port->ip_baud = 9600;
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port->ip_control = control;
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port->ip_mem = ioc4_misc;
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@ -2733,9 +2739,8 @@ ioc4_serial_attach_one(struct ioc4_driver_data *idd)
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"%s : request_irq fails for IRQ 0x%x\n ",
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__FUNCTION__, idd->idd_pdev->irq);
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}
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if ((ret = ioc4_attach_local(idd->idd_pdev, control, soft,
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soft->is_ioc4_misc_addr,
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soft->is_ioc4_serial_addr)))
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ret = ioc4_attach_local(idd);
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if (ret)
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goto out4;
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/* register port with the serial core */
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@ -6,7 +6,7 @@ menu "SN Devices"
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config SGI_IOC4
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tristate "SGI IOC4 Base IO support"
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depends on IA64_GENERIC || IA64_SGI_SN2
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depends on (IA64_GENERIC || IA64_SGI_SN2) && MMTIMER
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default m
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---help---
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This option enables basic support for the SGI IOC4-based Base IO
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@ -29,7 +29,26 @@
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/ioc4.h>
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#include <linux/mmtimer.h>
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#include <linux/rtc.h>
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#include <linux/rwsem.h>
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#include <asm/sn/addrs.h>
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#include <asm/sn/clksupport.h>
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#include <asm/sn/shub_mmr.h>
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/***************
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* Definitions *
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***************/
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/* Tweakable values */
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/* PCI bus speed detection/calibration */
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#define IOC4_CALIBRATE_COUNT 63 /* Calibration cycle period */
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#define IOC4_CALIBRATE_CYCLES 256 /* Average over this many cycles */
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#define IOC4_CALIBRATE_DISCARD 2 /* Discard first few cycles */
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#define IOC4_CALIBRATE_LOW_MHZ 25 /* Lower bound on bus speed sanity */
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#define IOC4_CALIBRATE_HIGH_MHZ 75 /* Upper bound on bus speed sanity */
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#define IOC4_CALIBRATE_DEFAULT_MHZ 66 /* Assumed if sanity check fails */
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/************************
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* Submodule management *
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@ -101,6 +120,112 @@ ioc4_unregister_submodule(struct ioc4_submodule *is)
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* Device management *
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*********************/
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#define IOC4_CALIBRATE_LOW_LIMIT \
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(1000*IOC4_EXTINT_COUNT_DIVISOR/IOC4_CALIBRATE_LOW_MHZ)
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#define IOC4_CALIBRATE_HIGH_LIMIT \
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(1000*IOC4_EXTINT_COUNT_DIVISOR/IOC4_CALIBRATE_HIGH_MHZ)
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#define IOC4_CALIBRATE_DEFAULT \
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(1000*IOC4_EXTINT_COUNT_DIVISOR/IOC4_CALIBRATE_DEFAULT_MHZ)
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#define IOC4_CALIBRATE_END \
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(IOC4_CALIBRATE_CYCLES + IOC4_CALIBRATE_DISCARD)
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#define IOC4_INT_OUT_MODE_TOGGLE 0x7 /* Toggle INT_OUT every COUNT+1 ticks */
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/* Determines external interrupt output clock period of the PCI bus an
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* IOC4 is attached to. This value can be used to determine the PCI
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* bus speed.
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*
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* IOC4 has a design feature that various internal timers are derived from
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* the PCI bus clock. This causes IOC4 device drivers to need to take the
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* bus speed into account when setting various register values (e.g. INT_OUT
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* register COUNT field, UART divisors, etc). Since this information is
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* needed by several subdrivers, it is determined by the main IOC4 driver,
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* even though the following code utilizes external interrupt registers
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* to perform the speed calculation.
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*/
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static void
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ioc4_clock_calibrate(struct ioc4_driver_data *idd)
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{
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extern unsigned long sn_rtc_cycles_per_second;
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union ioc4_int_out int_out;
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union ioc4_gpcr gpcr;
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unsigned int state, last_state = 1;
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uint64_t start = 0, end, period;
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unsigned int count = 0;
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/* Enable output */
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gpcr.raw = 0;
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gpcr.fields.dir = IOC4_GPCR_DIR_0;
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gpcr.fields.int_out_en = 1;
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writel(gpcr.raw, &idd->idd_misc_regs->gpcr_s.raw);
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/* Reset to power-on state */
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writel(0, &idd->idd_misc_regs->int_out.raw);
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mmiowb();
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printk(KERN_INFO
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"%s: Calibrating PCI bus speed "
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"for pci_dev %s ... ", __FUNCTION__, pci_name(idd->idd_pdev));
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/* Set up square wave */
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int_out.raw = 0;
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int_out.fields.count = IOC4_CALIBRATE_COUNT;
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int_out.fields.mode = IOC4_INT_OUT_MODE_TOGGLE;
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int_out.fields.diag = 0;
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writel(int_out.raw, &idd->idd_misc_regs->int_out.raw);
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mmiowb();
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/* Check square wave period averaged over some number of cycles */
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do {
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int_out.raw = readl(&idd->idd_misc_regs->int_out.raw);
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state = int_out.fields.int_out;
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if (!last_state && state) {
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count++;
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if (count == IOC4_CALIBRATE_END) {
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end = rtc_time();
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break;
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} else if (count == IOC4_CALIBRATE_DISCARD)
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start = rtc_time();
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}
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last_state = state;
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} while (1);
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/* Calculation rearranged to preserve intermediate precision.
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* Logically:
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* 1. "end - start" gives us number of RTC cycles over all the
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* square wave cycles measured.
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* 2. Divide by number of square wave cycles to get number of
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* RTC cycles per square wave cycle.
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* 3. Divide by 2*(int_out.fields.count+1), which is the formula
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* by which the IOC4 generates the square wave, to get the
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* number of RTC cycles per IOC4 INT_OUT count.
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* 4. Divide by sn_rtc_cycles_per_second to get seconds per
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* count.
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* 5. Multiply by 1E9 to get nanoseconds per count.
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*/
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period = ((end - start) * 1000000000) /
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(IOC4_CALIBRATE_CYCLES * 2 * (IOC4_CALIBRATE_COUNT + 1)
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* sn_rtc_cycles_per_second);
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/* Bounds check the result. */
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if (period > IOC4_CALIBRATE_LOW_LIMIT ||
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period < IOC4_CALIBRATE_HIGH_LIMIT) {
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printk("failed. Assuming PCI clock ticks are %d ns.\n",
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IOC4_CALIBRATE_DEFAULT / IOC4_EXTINT_COUNT_DIVISOR);
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period = IOC4_CALIBRATE_DEFAULT;
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} else {
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printk("succeeded. PCI clock ticks are %ld ns.\n",
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period / IOC4_EXTINT_COUNT_DIVISOR);
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}
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/* Remember results. We store the extint clock period rather
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* than the PCI clock period so that greater precision is
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* retained. Divide by IOC4_EXTINT_COUNT_DIVISOR to get
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* PCI clock period.
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*/
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idd->count_period = period;
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}
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/* Adds a new instance of an IOC4 card */
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static int
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ioc4_probe(struct pci_dev *pdev, const struct pci_device_id *pci_id)
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@ -170,6 +295,9 @@ ioc4_probe(struct pci_dev *pdev, const struct pci_device_id *pci_id)
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pci_write_config_dword(idd->idd_pdev, PCI_COMMAND,
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pcmd | PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
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/* Determine PCI clock */
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ioc4_clock_calibrate(idd);
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/* Disable/clear all interrupts. Need to do this here lest
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* one submodule request the shared IOC4 IRQ, but interrupt
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* is generated by a different subdevice.
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@ -11,6 +11,14 @@
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#include <linux/interrupt.h>
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/***************
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* Definitions *
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***************/
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/* Miscellaneous values inherent to hardware */
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#define IOC4_EXTINT_COUNT_DIVISOR 520 /* PCI clocks per COUNT tick */
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/***********************************
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* Structures needed by subdrivers *
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***********************************/
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@ -119,19 +127,34 @@ struct ioc4_misc_regs {
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} gppr[8]; /* Generic PIO pins */
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};
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/* One of these per IOC4
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*
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* The idd_serial_data field is present here, even though it's used
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* solely by the serial subdriver, because the main IOC4 module
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* properly owns pci_{get,set}_drvdata functionality. This field
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* allows that subdriver to stash its own drvdata somewhere.
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*/
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/* Masks for GPCR DIR pins */
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#define IOC4_GPCR_DIR_0 0x01 /* External interrupt output */
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#define IOC4_GPCR_DIR_1 0x02 /* External interrupt input */
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#define IOC4_GPCR_DIR_2 0x04
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#define IOC4_GPCR_DIR_3 0x08 /* Keyboard/mouse presence */
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#define IOC4_GPCR_DIR_4 0x10 /* Ser. port 0 xcvr select (0=232, 1=422) */
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#define IOC4_GPCR_DIR_5 0x20 /* Ser. port 1 xcvr select (0=232, 1=422) */
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#define IOC4_GPCR_DIR_6 0x40 /* Ser. port 2 xcvr select (0=232, 1=422) */
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#define IOC4_GPCR_DIR_7 0x80 /* Ser. port 3 xcvr select (0=232, 1=422) */
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/* Masks for GPCR EDGE pins */
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#define IOC4_GPCR_EDGE_0 0x01
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#define IOC4_GPCR_EDGE_1 0x02 /* External interrupt input */
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#define IOC4_GPCR_EDGE_2 0x04
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#define IOC4_GPCR_EDGE_3 0x08
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#define IOC4_GPCR_EDGE_4 0x10
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#define IOC4_GPCR_EDGE_5 0x20
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#define IOC4_GPCR_EDGE_6 0x40
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#define IOC4_GPCR_EDGE_7 0x80
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/* One of these per IOC4 */
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struct ioc4_driver_data {
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struct list_head idd_list;
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unsigned long idd_bar0;
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struct pci_dev *idd_pdev;
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const struct pci_device_id *idd_pci_id;
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struct __iomem ioc4_misc_regs *idd_misc_regs;
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unsigned long count_period;
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void *idd_serial_data;
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};
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