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e1000: add ich8lan core functions
This implements the core new functions needed for ich8's internal NIC. This includes: * ich8 specific read/write code * flash/nvm access code * software semaphore flag functions * 10/100 PHY (fe - no gigabit speed) support for low-end versions * A workaround for a powerdown sequence problem discovered that affects a small number of motherboard. Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com>
This commit is contained in:
Auke Kok
Auke Kok
parent
ab7bc0ad72
commit
d37ea5d562
3 changed files with 1392 additions and 7 deletions
File diff suppressed because it is too large
Load diff
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@ -62,6 +62,7 @@ typedef enum {
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e1000_82572,
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e1000_82573,
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e1000_80003es2lan,
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e1000_ich8lan,
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e1000_num_macs
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} e1000_mac_type;
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@ -70,6 +71,7 @@ typedef enum {
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e1000_eeprom_spi,
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e1000_eeprom_microwire,
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e1000_eeprom_flash,
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e1000_eeprom_ich8,
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e1000_eeprom_none, /* No NVM support */
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e1000_num_eeprom_types
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} e1000_eeprom_type;
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@ -98,6 +100,11 @@ typedef enum {
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e1000_fc_default = 0xFF
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} e1000_fc_type;
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struct e1000_shadow_ram {
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uint16_t eeprom_word;
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boolean_t modified;
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};
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/* PCI bus types */
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typedef enum {
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e1000_bus_type_unknown = 0,
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@ -218,6 +225,8 @@ typedef enum {
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e1000_phy_igp,
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e1000_phy_igp_2,
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e1000_phy_gg82563,
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e1000_phy_igp_3,
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e1000_phy_ife,
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e1000_phy_undefined = 0xFF
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} e1000_phy_type;
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@ -313,6 +322,10 @@ int32_t e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy
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int32_t e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
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int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
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int32_t e1000_phy_reset(struct e1000_hw *hw);
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void e1000_phy_powerdown_workaround(struct e1000_hw *hw);
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int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
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int32_t e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size);
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int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw);
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int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
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int32_t e1000_validate_mdi_setting(struct e1000_hw *hw);
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int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data);
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@ -331,6 +344,7 @@ uint32_t e1000_enable_mng_pass_thru(struct e1000_hw *hw);
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#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */
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#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */
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#define E1000_MNG_IAMT_MODE 0x3
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#define E1000_MNG_ICH_IAMT_MODE 0x2
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#define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */
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#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */
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@ -388,6 +402,8 @@ int32_t e1000_read_part_num(struct e1000_hw *hw, uint32_t * part_num);
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int32_t e1000_read_mac_addr(struct e1000_hw * hw);
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int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
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void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
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void e1000_release_software_flag(struct e1000_hw *hw);
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int32_t e1000_get_software_flag(struct e1000_hw *hw);
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/* Filters (multicast, vlan, receive) */
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void e1000_mc_addr_list_update(struct e1000_hw *hw, uint8_t * mc_addr_list, uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count);
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@ -423,6 +439,29 @@ int32_t e1000_disable_pciex_master(struct e1000_hw *hw);
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int32_t e1000_get_software_semaphore(struct e1000_hw *hw);
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void e1000_release_software_semaphore(struct e1000_hw *hw);
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int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
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int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop);
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int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index,
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uint8_t *data);
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int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index,
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uint8_t byte);
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int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index,
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uint8_t byte);
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int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index,
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uint16_t *data);
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int32_t e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
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uint32_t size, uint16_t *data);
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int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset,
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uint16_t words, uint16_t *data);
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int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset,
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uint16_t words, uint16_t *data);
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int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t segment);
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#define E1000_READ_REG_IO(a, reg) \
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e1000_read_reg_io((a), E1000_##reg)
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#define E1000_WRITE_REG_IO(a, reg, val) \
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e1000_write_reg_io((a), E1000_##reg, val)
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/* PCI Device IDs */
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#define E1000_DEV_ID_82542 0x1000
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@ -447,6 +486,7 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
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#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
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#define E1000_DEV_ID_82541EI 0x1013
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#define E1000_DEV_ID_82541EI_MOBILE 0x1018
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#define E1000_DEV_ID_82541ER_LOM 0x1014
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#define E1000_DEV_ID_82541ER 0x1078
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#define E1000_DEV_ID_82547GI 0x1075
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#define E1000_DEV_ID_82541GI 0x1076
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@ -458,18 +498,28 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
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#define E1000_DEV_ID_82546GB_PCIE 0x108A
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#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
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#define E1000_DEV_ID_82547EI 0x1019
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#define E1000_DEV_ID_82547EI_MOBILE 0x101A
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#define E1000_DEV_ID_82571EB_COPPER 0x105E
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#define E1000_DEV_ID_82571EB_FIBER 0x105F
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#define E1000_DEV_ID_82571EB_SERDES 0x1060
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#define E1000_DEV_ID_82572EI_COPPER 0x107D
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#define E1000_DEV_ID_82572EI_FIBER 0x107E
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#define E1000_DEV_ID_82572EI_SERDES 0x107F
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#define E1000_DEV_ID_82572EI 0x10B9
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#define E1000_DEV_ID_82573E 0x108B
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#define E1000_DEV_ID_82573E_IAMT 0x108C
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#define E1000_DEV_ID_82573L 0x109A
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#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
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#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
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#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
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#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
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#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
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#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
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#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
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#define E1000_DEV_ID_ICH8_IGP_C 0x104B
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#define E1000_DEV_ID_ICH8_IFE 0x104C
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#define E1000_DEV_ID_ICH8_IGP_M 0x104D
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#define NODE_ADDRESS_SIZE 6
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@ -540,6 +590,14 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
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E1000_IMS_RXSEQ | \
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E1000_IMS_LSC)
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/* Additional interrupts need to be handled for e1000_ich8lan:
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DSW = The FW changed the status of the DISSW bit in FWSM
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PHYINT = The LAN connected device generates an interrupt
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EPRST = Manageability reset event */
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#define IMS_ICH8LAN_ENABLE_MASK (\
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E1000_IMS_DSW | \
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E1000_IMS_PHYINT | \
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E1000_IMS_EPRST)
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/* Number of high/low register pairs in the RAR. The RAR (Receive Address
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* Registers) holds the directed and multicast addresses that we monitor. We
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@ -547,6 +605,7 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
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* E1000_RAR_ENTRIES - 1 multicast addresses.
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*/
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#define E1000_RAR_ENTRIES 15
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#define E1000_RAR_ENTRIES_ICH8LAN 7
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#define MIN_NUMBER_OF_DESCRIPTORS 8
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#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
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@ -768,6 +827,9 @@ struct e1000_data_desc {
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#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
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#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
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#define E1000_NUM_UNICAST_ICH8LAN 7
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#define E1000_MC_TBL_SIZE_ICH8LAN 32
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/* Receive Address Register */
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struct e1000_rar {
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@ -777,6 +839,7 @@ struct e1000_rar {
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/* Number of entries in the Multicast Table Array (MTA). */
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#define E1000_NUM_MTA_REGISTERS 128
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#define E1000_NUM_MTA_REGISTERS_ICH8LAN 32
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/* IPv4 Address Table Entry */
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struct e1000_ipv4_at_entry {
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@ -787,6 +850,7 @@ struct e1000_ipv4_at_entry {
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/* Four wakeup IP addresses are supported */
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#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
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#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
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#define E1000_IP4AT_SIZE_ICH8LAN 3
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#define E1000_IP6AT_SIZE 1
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/* IPv6 Address Table Entry */
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@ -845,6 +909,7 @@ struct e1000_ffvt_entry {
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#define E1000_FLA 0x0001C /* Flash Access - RW */
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#define E1000_MDIC 0x00020 /* MDI Control - RW */
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#define E1000_SCTL 0x00024 /* SerDes Control - RW */
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#define E1000_FEXTNVM 0x00028 /* Future Extended NVM register */
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#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
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#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
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#define E1000_FCT 0x00030 /* Flow Control Type - RW */
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@ -873,6 +938,8 @@ struct e1000_ffvt_entry {
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#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
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#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
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#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
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#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
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#define FEXTNVM_SW_CONFIG 0x0001
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#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
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#define E1000_PBS 0x01008 /* Packet Buffer Size */
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#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
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@ -900,11 +967,13 @@ struct e1000_ffvt_entry {
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#define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */
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#define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */
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#define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */
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#define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */
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#define E1000_RXDCTL 0x02828 /* RX Descriptor Control queue 0 - RW */
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#define E1000_RXDCTL1 0x02928 /* RX Descriptor Control queue 1 - RW */
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#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
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#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
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#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
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#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
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#define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */
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#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
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#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
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#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
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@ -1051,6 +1120,7 @@ struct e1000_ffvt_entry {
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#define E1000_82542_FLA E1000_FLA
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#define E1000_82542_MDIC E1000_MDIC
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#define E1000_82542_SCTL E1000_SCTL
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#define E1000_82542_FEXTNVM E1000_FEXTNVM
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#define E1000_82542_FCAL E1000_FCAL
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#define E1000_82542_FCAH E1000_FCAH
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#define E1000_82542_FCT E1000_FCT
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@ -1074,6 +1144,19 @@ struct e1000_ffvt_entry {
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#define E1000_82542_RDLEN0 E1000_82542_RDLEN
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#define E1000_82542_RDH0 E1000_82542_RDH
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#define E1000_82542_RDT0 E1000_82542_RDT
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#define E1000_82542_SRRCTL(_n) (0x280C + ((_n) << 8)) /* Split and Replication
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* RX Control - RW */
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#define E1000_82542_DCA_RXCTRL(_n) (0x02814 + ((_n) << 8))
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#define E1000_82542_RDBAH3 0x02B04 /* RX Desc Base High Queue 3 - RW */
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#define E1000_82542_RDBAL3 0x02B00 /* RX Desc Low Queue 3 - RW */
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#define E1000_82542_RDLEN3 0x02B08 /* RX Desc Length Queue 3 - RW */
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#define E1000_82542_RDH3 0x02B10 /* RX Desc Head Queue 3 - RW */
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#define E1000_82542_RDT3 0x02B18 /* RX Desc Tail Queue 3 - RW */
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#define E1000_82542_RDBAL2 0x02A00 /* RX Desc Base Low Queue 2 - RW */
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#define E1000_82542_RDBAH2 0x02A04 /* RX Desc Base High Queue 2 - RW */
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#define E1000_82542_RDLEN2 0x02A08 /* RX Desc Length Queue 2 - RW */
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#define E1000_82542_RDH2 0x02A10 /* RX Desc Head Queue 2 - RW */
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#define E1000_82542_RDT2 0x02A18 /* RX Desc Tail Queue 2 - RW */
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#define E1000_82542_RDTR1 0x00130
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#define E1000_82542_RDBAL1 0x00138
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#define E1000_82542_RDBAH1 0x0013C
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@ -1111,11 +1194,14 @@ struct e1000_ffvt_entry {
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#define E1000_82542_FLOP E1000_FLOP
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#define E1000_82542_EXTCNF_CTRL E1000_EXTCNF_CTRL
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#define E1000_82542_EXTCNF_SIZE E1000_EXTCNF_SIZE
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#define E1000_82542_PHY_CTRL E1000_PHY_CTRL
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#define E1000_82542_ERT E1000_ERT
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#define E1000_82542_RXDCTL E1000_RXDCTL
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#define E1000_82542_RXDCTL1 E1000_RXDCTL1
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#define E1000_82542_RADV E1000_RADV
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#define E1000_82542_RSRPD E1000_RSRPD
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#define E1000_82542_TXDMAC E1000_TXDMAC
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#define E1000_82542_KABGTXD E1000_KABGTXD
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#define E1000_82542_TDFHS E1000_TDFHS
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#define E1000_82542_TDFTS E1000_TDFTS
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#define E1000_82542_TDFPC E1000_TDFPC
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@ -1311,13 +1397,16 @@ struct e1000_hw_stats {
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/* Structure containing variables used by the shared code (e1000_hw.c) */
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struct e1000_hw {
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uint8_t __iomem *hw_addr;
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uint8_t *hw_addr;
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uint8_t *flash_address;
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e1000_mac_type mac_type;
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e1000_phy_type phy_type;
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uint32_t phy_init_script;
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e1000_media_type media_type;
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void *back;
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struct e1000_shadow_ram *eeprom_shadow_ram;
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uint32_t flash_bank_size;
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uint32_t flash_base_addr;
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e1000_fc_type fc;
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e1000_bus_speed bus_speed;
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e1000_bus_width bus_width;
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@ -1329,6 +1418,7 @@ struct e1000_hw {
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uint32_t asf_firmware_present;
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uint32_t eeprom_semaphore_present;
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uint32_t swfw_sync_present;
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uint32_t swfwhw_semaphore_present;
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unsigned long io_base;
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uint32_t phy_id;
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uint32_t phy_revision;
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@ -1388,6 +1478,7 @@ struct e1000_hw {
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boolean_t in_ifs_mode;
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boolean_t mng_reg_access_disabled;
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boolean_t leave_av_bit_off;
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boolean_t kmrn_lock_loss_workaround_disabled;
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};
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@ -1436,6 +1527,7 @@ struct e1000_hw {
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#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
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#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
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#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
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#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */
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/* Device Status */
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#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
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@ -1450,6 +1542,8 @@ struct e1000_hw {
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#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
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#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
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#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
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#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion
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by EEPROM/Flash */
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#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
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#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */
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#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */
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@ -1507,6 +1601,10 @@ struct e1000_hw {
|
|||
#define E1000_STM_OPCODE 0xDB00
|
||||
#define E1000_HICR_FW_RESET 0xC0
|
||||
|
||||
#define E1000_SHADOW_RAM_WORDS 2048
|
||||
#define E1000_ICH8_NVM_SIG_WORD 0x13
|
||||
#define E1000_ICH8_NVM_SIG_MASK 0xC0
|
||||
|
||||
/* EEPROM Read */
|
||||
#define E1000_EERD_START 0x00000001 /* Start Read */
|
||||
#define E1000_EERD_DONE 0x00000010 /* Read Done */
|
||||
|
|
@ -1552,7 +1650,6 @@ struct e1000_hw {
|
|||
#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
|
||||
#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
|
||||
#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
|
||||
#define E1000_CTRL_EXT_CANC 0x04000000 /* Interrupt delay cancellation */
|
||||
#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
|
||||
#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */
|
||||
#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */
|
||||
|
|
@ -1592,12 +1689,31 @@ struct e1000_hw {
|
|||
#define E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800
|
||||
|
||||
/* In-Band Control */
|
||||
#define E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT 0x00000500
|
||||
#define E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010
|
||||
|
||||
/* Half-Duplex Control */
|
||||
#define E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004
|
||||
#define E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000
|
||||
|
||||
#define E1000_KUMCTRLSTA_OFFSET_K0S_CTRL 0x0000001E
|
||||
|
||||
#define E1000_KUMCTRLSTA_DIAG_FELPBK 0x2000
|
||||
#define E1000_KUMCTRLSTA_DIAG_NELPBK 0x1000
|
||||
|
||||
#define E1000_KUMCTRLSTA_K0S_100_EN 0x2000
|
||||
#define E1000_KUMCTRLSTA_K0S_GBE_EN 0x1000
|
||||
#define E1000_KUMCTRLSTA_K0S_ENTRY_LATENCY_MASK 0x0003
|
||||
|
||||
#define E1000_KABGTXD_BGSQLBIAS 0x00050000
|
||||
|
||||
#define E1000_PHY_CTRL_SPD_EN 0x00000001
|
||||
#define E1000_PHY_CTRL_D0A_LPLU 0x00000002
|
||||
#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
|
||||
#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
|
||||
#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
|
||||
#define E1000_PHY_CTRL_B2B_EN 0x00000080
|
||||
|
||||
/* LED Control */
|
||||
#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
|
||||
#define E1000_LEDCTL_LED0_MODE_SHIFT 0
|
||||
|
|
@ -1667,6 +1783,9 @@ struct e1000_hw {
|
|||
#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */
|
||||
#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */
|
||||
#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */
|
||||
#define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW bit in the FWSM */
|
||||
#define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */
|
||||
#define E1000_ICR_EPRST 0x00100000 /* ME handware reset occurs */
|
||||
|
||||
/* Interrupt Cause Set */
|
||||
#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
|
||||
|
|
@ -1693,6 +1812,9 @@ struct e1000_hw {
|
|||
#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
|
||||
#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
|
||||
#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
|
||||
#define E1000_ICS_DSW E1000_ICR_DSW
|
||||
#define E1000_ICS_PHYINT E1000_ICR_PHYINT
|
||||
#define E1000_ICS_EPRST E1000_ICR_EPRST
|
||||
|
||||
/* Interrupt Mask Set */
|
||||
#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
|
||||
|
|
@ -1719,6 +1841,9 @@ struct e1000_hw {
|
|||
#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
|
||||
#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
|
||||
#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
|
||||
#define E1000_IMS_DSW E1000_ICR_DSW
|
||||
#define E1000_IMS_PHYINT E1000_ICR_PHYINT
|
||||
#define E1000_IMS_EPRST E1000_ICR_EPRST
|
||||
|
||||
/* Interrupt Mask Clear */
|
||||
#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
|
||||
|
|
@ -1745,6 +1870,9 @@ struct e1000_hw {
|
|||
#define E1000_IMC_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
|
||||
#define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
|
||||
#define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
|
||||
#define E1000_IMC_DSW E1000_ICR_DSW
|
||||
#define E1000_IMC_PHYINT E1000_ICR_PHYINT
|
||||
#define E1000_IMC_EPRST E1000_ICR_EPRST
|
||||
|
||||
/* Receive Control */
|
||||
#define E1000_RCTL_RST 0x00000001 /* Software reset */
|
||||
|
|
@ -1919,9 +2047,10 @@ struct e1000_hw {
|
|||
#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
|
||||
#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
|
||||
#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
|
||||
#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00040000
|
||||
#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
|
||||
#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
|
||||
#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
|
||||
#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
|
||||
|
||||
/* Definitions for power management and wakeup registers */
|
||||
/* Wake Up Control */
|
||||
|
|
@ -2011,6 +2140,15 @@ struct e1000_hw {
|
|||
#define E1000_FWSM_MODE_SHIFT 1
|
||||
#define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */
|
||||
|
||||
#define E1000_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */
|
||||
#define E1000_FWSM_DISSW 0x10000000 /* FW disable SW Write Access */
|
||||
#define E1000_FWSM_SKUSEL_MASK 0x60000000 /* LAN SKU select */
|
||||
#define E1000_FWSM_SKUEL_SHIFT 29
|
||||
#define E1000_FWSM_SKUSEL_EMB 0x0 /* Embedded SKU */
|
||||
#define E1000_FWSM_SKUSEL_CONS 0x1 /* Consumer SKU */
|
||||
#define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */
|
||||
#define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */
|
||||
|
||||
/* FFLT Debug Register */
|
||||
#define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */
|
||||
|
||||
|
|
@ -2083,6 +2221,8 @@ struct e1000_host_command_info {
|
|||
E1000_GCR_TXDSCW_NO_SNOOP | \
|
||||
E1000_GCR_TXDSCR_NO_SNOOP)
|
||||
|
||||
#define PCI_EX_82566_SNOOP_ALL PCI_EX_NO_SNOOP_ALL
|
||||
|
||||
#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
|
||||
/* Function Active and Power State to MNG */
|
||||
#define E1000_FACTPS_FUNC0_POWER_STATE_MASK 0x00000003
|
||||
|
|
@ -2141,8 +2281,10 @@ struct e1000_host_command_info {
|
|||
#define EEPROM_PHY_CLASS_WORD 0x0007
|
||||
#define EEPROM_INIT_CONTROL1_REG 0x000A
|
||||
#define EEPROM_INIT_CONTROL2_REG 0x000F
|
||||
#define EEPROM_SWDEF_PINS_CTRL_PORT_1 0x0010
|
||||
#define EEPROM_INIT_CONTROL3_PORT_B 0x0014
|
||||
#define EEPROM_INIT_3GIO_3 0x001A
|
||||
#define EEPROM_SWDEF_PINS_CTRL_PORT_0 0x0020
|
||||
#define EEPROM_INIT_CONTROL3_PORT_A 0x0024
|
||||
#define EEPROM_CFG 0x0012
|
||||
#define EEPROM_FLASH_VERSION 0x0032
|
||||
|
|
@ -2154,10 +2296,16 @@ struct e1000_host_command_info {
|
|||
/* Word definitions for ID LED Settings */
|
||||
#define ID_LED_RESERVED_0000 0x0000
|
||||
#define ID_LED_RESERVED_FFFF 0xFFFF
|
||||
#define ID_LED_RESERVED_82573 0xF746
|
||||
#define ID_LED_DEFAULT_82573 0x1811
|
||||
#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
|
||||
(ID_LED_OFF1_OFF2 << 8) | \
|
||||
(ID_LED_DEF1_DEF2 << 4) | \
|
||||
(ID_LED_DEF1_DEF2))
|
||||
#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
|
||||
(ID_LED_DEF1_OFF2 << 8) | \
|
||||
(ID_LED_DEF1_ON2 << 4) | \
|
||||
(ID_LED_DEF1_DEF2))
|
||||
#define ID_LED_DEF1_DEF2 0x1
|
||||
#define ID_LED_DEF1_ON2 0x2
|
||||
#define ID_LED_DEF1_OFF2 0x3
|
||||
|
|
@ -2192,6 +2340,11 @@ struct e1000_host_command_info {
|
|||
#define EEPROM_WORD0F_ASM_DIR 0x2000
|
||||
#define EEPROM_WORD0F_ANE 0x0800
|
||||
#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
|
||||
#define EEPROM_WORD0F_LPLU 0x0001
|
||||
|
||||
/* Mask bits for fields in Word 0x10/0x20 of the EEPROM */
|
||||
#define EEPROM_WORD1020_GIGA_DISABLE 0x0010
|
||||
#define EEPROM_WORD1020_GIGA_DISABLE_NON_D0A 0x0008
|
||||
|
||||
/* Mask bits for fields in Word 0x1a of the EEPROM */
|
||||
#define EEPROM_WORD1A_ASPM_MASK 0x000C
|
||||
|
|
@ -2266,23 +2419,29 @@ struct e1000_host_command_info {
|
|||
#define E1000_EXTCNF_CTRL_D_UD_OWNER 0x00000010
|
||||
#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
|
||||
#define E1000_EXTCNF_CTRL_MDIO_HW_OWNERSHIP 0x00000040
|
||||
#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER 0x1FFF0000
|
||||
#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER 0x0FFF0000
|
||||
|
||||
#define E1000_EXTCNF_SIZE_EXT_PHY_LENGTH 0x000000FF
|
||||
#define E1000_EXTCNF_SIZE_EXT_DOCK_LENGTH 0x0000FF00
|
||||
#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH 0x00FF0000
|
||||
#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
|
||||
#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
|
||||
|
||||
/* PBA constants */
|
||||
#define E1000_PBA_8K 0x0008 /* 8KB, default Rx allocation */
|
||||
#define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */
|
||||
#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
|
||||
#define E1000_PBA_22K 0x0016
|
||||
#define E1000_PBA_24K 0x0018
|
||||
#define E1000_PBA_30K 0x001E
|
||||
#define E1000_PBA_32K 0x0020
|
||||
#define E1000_PBA_34K 0x0022
|
||||
#define E1000_PBA_38K 0x0026
|
||||
#define E1000_PBA_40K 0x0028
|
||||
#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
|
||||
|
||||
#define E1000_PBS_16K E1000_PBA_16K
|
||||
|
||||
/* Flow Control Constants */
|
||||
#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
|
||||
#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
|
||||
|
|
@ -2337,7 +2496,7 @@ struct e1000_host_command_info {
|
|||
/* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */
|
||||
#define AUTO_READ_DONE_TIMEOUT 10
|
||||
/* Number of milliseconds we wait for PHY configuration done after MAC reset */
|
||||
#define PHY_CFG_TIMEOUT 40
|
||||
#define PHY_CFG_TIMEOUT 100
|
||||
|
||||
#define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
|
||||
|
||||
|
|
@ -3002,6 +3161,221 @@ struct e1000_host_command_info {
|
|||
#define L1LXT971A_PHY_ID 0x001378E0
|
||||
#define GG82563_E_PHY_ID 0x01410CA0
|
||||
|
||||
|
||||
/* Bits...
|
||||
* 15-5: page
|
||||
* 4-0: register offset
|
||||
*/
|
||||
#define PHY_PAGE_SHIFT 5
|
||||
#define PHY_REG(page, reg) \
|
||||
(((page) << PHY_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
|
||||
|
||||
#define IGP3_PHY_PORT_CTRL \
|
||||
PHY_REG(769, 17) /* Port General Configuration */
|
||||
#define IGP3_PHY_RATE_ADAPT_CTRL \
|
||||
PHY_REG(769, 25) /* Rate Adapter Control Register */
|
||||
|
||||
#define IGP3_KMRN_FIFO_CTRL_STATS \
|
||||
PHY_REG(770, 16) /* KMRN FIFO's control/status register */
|
||||
#define IGP3_KMRN_POWER_MNG_CTRL \
|
||||
PHY_REG(770, 17) /* KMRN Power Management Control Register */
|
||||
#define IGP3_KMRN_INBAND_CTRL \
|
||||
PHY_REG(770, 18) /* KMRN Inband Control Register */
|
||||
#define IGP3_KMRN_DIAG \
|
||||
PHY_REG(770, 19) /* KMRN Diagnostic register */
|
||||
#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 /* RX PCS is not synced */
|
||||
#define IGP3_KMRN_ACK_TIMEOUT \
|
||||
PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */
|
||||
|
||||
#define IGP3_VR_CTRL \
|
||||
PHY_REG(776, 18) /* Voltage regulator control register */
|
||||
#define IGP3_VR_CTRL_MODE_SHUT 0x0200 /* Enter powerdown, shutdown VRs */
|
||||
|
||||
#define IGP3_CAPABILITY \
|
||||
PHY_REG(776, 19) /* IGP3 Capability Register */
|
||||
|
||||
/* Capabilities for SKU Control */
|
||||
#define IGP3_CAP_INITIATE_TEAM 0x0001 /* Able to initiate a team */
|
||||
#define IGP3_CAP_WFM 0x0002 /* Support WoL and PXE */
|
||||
#define IGP3_CAP_ASF 0x0004 /* Support ASF */
|
||||
#define IGP3_CAP_LPLU 0x0008 /* Support Low Power Link Up */
|
||||
#define IGP3_CAP_DC_AUTO_SPEED 0x0010 /* Support AC/DC Auto Link Speed */
|
||||
#define IGP3_CAP_SPD 0x0020 /* Support Smart Power Down */
|
||||
#define IGP3_CAP_MULT_QUEUE 0x0040 /* Support 2 tx & 2 rx queues */
|
||||
#define IGP3_CAP_RSS 0x0080 /* Support RSS */
|
||||
#define IGP3_CAP_8021PQ 0x0100 /* Support 802.1Q & 802.1p */
|
||||
#define IGP3_CAP_AMT_CB 0x0200 /* Support active manageability and circuit breaker */
|
||||
|
||||
#define IGP3_PPC_JORDAN_EN 0x0001
|
||||
#define IGP3_PPC_JORDAN_GIGA_SPEED 0x0002
|
||||
|
||||
#define IGP3_KMRN_PMC_EE_IDLE_LINK_DIS 0x0001
|
||||
#define IGP3_KMRN_PMC_K0S_ENTRY_LATENCY_MASK 0x001E
|
||||
#define IGP3_KMRN_PMC_K0S_MODE1_EN_GIGA 0x0020
|
||||
#define IGP3_KMRN_PMC_K0S_MODE1_EN_100 0x0040
|
||||
|
||||
#define IGP3E1000_PHY_MISC_CTRL 0x1B /* Misc. Ctrl register */
|
||||
#define IGP3_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Duplex Manual Set */
|
||||
|
||||
#define IGP3_KMRN_EXT_CTRL PHY_REG(770, 18)
|
||||
#define IGP3_KMRN_EC_DIS_INBAND 0x0080
|
||||
|
||||
#define IGP03E1000_E_PHY_ID 0x02A80390
|
||||
#define IFE_E_PHY_ID 0x02A80330 /* 10/100 PHY */
|
||||
#define IFE_PLUS_E_PHY_ID 0x02A80320
|
||||
#define IFE_C_E_PHY_ID 0x02A80310
|
||||
|
||||
#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 /* 100BaseTx Extended Status, Control and Address */
|
||||
#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special control register */
|
||||
#define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive False Carrier Counter */
|
||||
#define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnet Counter */
|
||||
#define IFE_PHY_RCV_ERROT_FRAME 0x15 /* 100BaseTx Receive Error Frame Counter */
|
||||
#define IFE_PHY_RCV_SYMBOL_ERR 0x16 /* Receive Symbol Error Counter */
|
||||
#define IFE_PHY_PREM_EOF_ERR 0x17 /* 100BaseTx Receive Premature End Of Frame Error Counter */
|
||||
#define IFE_PHY_RCV_EOF_ERR 0x18 /* 10BaseT Receive End Of Frame Error Counter */
|
||||
#define IFE_PHY_TX_JABBER_DETECT 0x19 /* 10BaseT Transmit Jabber Detect Counter */
|
||||
#define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and Status */
|
||||
#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY special control and LED configuration */
|
||||
#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */
|
||||
#define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control (HWI) */
|
||||
|
||||
#define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Defaut 1 = Disable auto reduced power down */
|
||||
#define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power state of 100BASE-TX */
|
||||
#define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power state of 10BASE-T */
|
||||
#define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T polarity */
|
||||
#define IFE_PESC_PHY_ADDR_MASK 0x007C /* Bit 6:2 for sampled PHY address */
|
||||
#define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed result 1=100Mbs, 0=10Mbs */
|
||||
#define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation duplex result 1=Full, 0=Half */
|
||||
#define IFE_PESC_POLARITY_REVERSED_SHIFT 8
|
||||
|
||||
#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* 1 = Dyanmic Power Down disabled */
|
||||
#define IFE_PSC_FORCE_POLARITY 0x0020 /* 1=Reversed Polarity, 0=Normal */
|
||||
#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity Disabled, 0=Enabled */
|
||||
#define IFE_PSC_JABBER_FUNC_DISABLE 0x0001 /* 1=Jabber Disabled, 0=Normal Jabber Operation */
|
||||
#define IFE_PSC_FORCE_POLARITY_SHIFT 5
|
||||
#define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT 4
|
||||
|
||||
#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X feature, default 0=disabled */
|
||||
#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X, 0=force MDI */
|
||||
#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
|
||||
#define IFE_PMC_AUTO_MDIX_COMPLETE 0x0010 /* Resolution algorthm is completed */
|
||||
#define IFE_PMC_MDIX_MODE_SHIFT 6
|
||||
#define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */
|
||||
|
||||
#define IFE_PHC_HWI_ENABLE 0x8000 /* Enable the HWI feature */
|
||||
#define IFE_PHC_ABILITY_CHECK 0x4000 /* 1= Test Passed, 0=failed */
|
||||
#define IFE_PHC_TEST_EXEC 0x2000 /* PHY launch test pulses on the wire */
|
||||
#define IFE_PHC_HIGHZ 0x0200 /* 1 = Open Circuit */
|
||||
#define IFE_PHC_LOWZ 0x0400 /* 1 = Short Circuit */
|
||||
#define IFE_PHC_LOW_HIGH_Z_MASK 0x0600 /* Mask for indication type of problem on the line */
|
||||
#define IFE_PHC_DISTANCE_MASK 0x01FF /* Mask for distance to the cable problem, in 80cm granularity */
|
||||
#define IFE_PHC_RESET_ALL_MASK 0x0000 /* Disable HWI */
|
||||
#define IFE_PSCL_PROBE_MODE 0x0020 /* LED Probe mode */
|
||||
#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
|
||||
#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
|
||||
|
||||
#define ICH8_FLASH_COMMAND_TIMEOUT 500 /* 500 ms , should be adjusted */
|
||||
#define ICH8_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles , should be adjusted */
|
||||
#define ICH8_FLASH_SEG_SIZE_256 256
|
||||
#define ICH8_FLASH_SEG_SIZE_4K 4096
|
||||
#define ICH8_FLASH_SEG_SIZE_64K 65536
|
||||
|
||||
#define ICH8_CYCLE_READ 0x0
|
||||
#define ICH8_CYCLE_RESERVED 0x1
|
||||
#define ICH8_CYCLE_WRITE 0x2
|
||||
#define ICH8_CYCLE_ERASE 0x3
|
||||
|
||||
#define ICH8_FLASH_GFPREG 0x0000
|
||||
#define ICH8_FLASH_HSFSTS 0x0004
|
||||
#define ICH8_FLASH_HSFCTL 0x0006
|
||||
#define ICH8_FLASH_FADDR 0x0008
|
||||
#define ICH8_FLASH_FDATA0 0x0010
|
||||
#define ICH8_FLASH_FRACC 0x0050
|
||||
#define ICH8_FLASH_FREG0 0x0054
|
||||
#define ICH8_FLASH_FREG1 0x0058
|
||||
#define ICH8_FLASH_FREG2 0x005C
|
||||
#define ICH8_FLASH_FREG3 0x0060
|
||||
#define ICH8_FLASH_FPR0 0x0074
|
||||
#define ICH8_FLASH_FPR1 0x0078
|
||||
#define ICH8_FLASH_SSFSTS 0x0090
|
||||
#define ICH8_FLASH_SSFCTL 0x0092
|
||||
#define ICH8_FLASH_PREOP 0x0094
|
||||
#define ICH8_FLASH_OPTYPE 0x0096
|
||||
#define ICH8_FLASH_OPMENU 0x0098
|
||||
|
||||
#define ICH8_FLASH_REG_MAPSIZE 0x00A0
|
||||
#define ICH8_FLASH_SECTOR_SIZE 4096
|
||||
#define ICH8_GFPREG_BASE_MASK 0x1FFF
|
||||
#define ICH8_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
|
||||
|
||||
/* ICH8 GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
|
||||
/* Offset 04h HSFSTS */
|
||||
union ich8_hws_flash_status {
|
||||
struct ich8_hsfsts {
|
||||
#ifdef E1000_BIG_ENDIAN
|
||||
uint16_t reserved2 :6;
|
||||
uint16_t fldesvalid :1;
|
||||
uint16_t flockdn :1;
|
||||
uint16_t flcdone :1;
|
||||
uint16_t flcerr :1;
|
||||
uint16_t dael :1;
|
||||
uint16_t berasesz :2;
|
||||
uint16_t flcinprog :1;
|
||||
uint16_t reserved1 :2;
|
||||
#else
|
||||
uint16_t flcdone :1; /* bit 0 Flash Cycle Done */
|
||||
uint16_t flcerr :1; /* bit 1 Flash Cycle Error */
|
||||
uint16_t dael :1; /* bit 2 Direct Access error Log */
|
||||
uint16_t berasesz :2; /* bit 4:3 Block/Sector Erase Size */
|
||||
uint16_t flcinprog :1; /* bit 5 flash SPI cycle in Progress */
|
||||
uint16_t reserved1 :2; /* bit 13:6 Reserved */
|
||||
uint16_t reserved2 :6; /* bit 13:6 Reserved */
|
||||
uint16_t fldesvalid :1; /* bit 14 Flash Descriptor Valid */
|
||||
uint16_t flockdn :1; /* bit 15 Flash Configuration Lock-Down */
|
||||
#endif
|
||||
} hsf_status;
|
||||
uint16_t regval;
|
||||
};
|
||||
|
||||
/* ICH8 GbE Flash Hardware Sequencing Flash control Register bit breakdown */
|
||||
/* Offset 06h FLCTL */
|
||||
union ich8_hws_flash_ctrl {
|
||||
struct ich8_hsflctl {
|
||||
#ifdef E1000_BIG_ENDIAN
|
||||
uint16_t fldbcount :2;
|
||||
uint16_t flockdn :6;
|
||||
uint16_t flcgo :1;
|
||||
uint16_t flcycle :2;
|
||||
uint16_t reserved :5;
|
||||
#else
|
||||
uint16_t flcgo :1; /* 0 Flash Cycle Go */
|
||||
uint16_t flcycle :2; /* 2:1 Flash Cycle */
|
||||
uint16_t reserved :5; /* 7:3 Reserved */
|
||||
uint16_t fldbcount :2; /* 9:8 Flash Data Byte Count */
|
||||
uint16_t flockdn :6; /* 15:10 Reserved */
|
||||
#endif
|
||||
} hsf_ctrl;
|
||||
uint16_t regval;
|
||||
};
|
||||
|
||||
/* ICH8 Flash Region Access Permissions */
|
||||
union ich8_hws_flash_regacc {
|
||||
struct ich8_flracc {
|
||||
#ifdef E1000_BIG_ENDIAN
|
||||
uint32_t gmwag :8;
|
||||
uint32_t gmrag :8;
|
||||
uint32_t grwa :8;
|
||||
uint32_t grra :8;
|
||||
#else
|
||||
uint32_t grra :8; /* 0:7 GbE region Read Access */
|
||||
uint32_t grwa :8; /* 8:15 GbE region Write Access */
|
||||
uint32_t gmrag :8; /* 23:16 GbE Master Read Access Grant */
|
||||
uint32_t gmwag :8; /* 31:24 GbE Master Write Access Grant */
|
||||
#endif
|
||||
} hsf_flregacc;
|
||||
uint16_t regval;
|
||||
};
|
||||
|
||||
/* Miscellaneous PHY bit definitions. */
|
||||
#define PHY_PREAMBLE 0xFFFFFFFF
|
||||
#define PHY_SOF 0x01
|
||||
|
|
|
|||
|
|
@ -127,4 +127,17 @@ typedef enum {
|
|||
|
||||
#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, STATUS)
|
||||
|
||||
#define E1000_WRITE_ICH8_REG(a, reg, value) ( \
|
||||
writel((value), ((a)->flash_address + reg)))
|
||||
|
||||
#define E1000_READ_ICH8_REG(a, reg) ( \
|
||||
readl((a)->flash_address + reg))
|
||||
|
||||
#define E1000_WRITE_ICH8_REG16(a, reg, value) ( \
|
||||
writew((value), ((a)->flash_address + reg)))
|
||||
|
||||
#define E1000_READ_ICH8_REG16(a, reg) ( \
|
||||
readw((a)->flash_address + reg))
|
||||
|
||||
|
||||
#endif /* _E1000_OSDEP_H_ */
|
||||
|
|
|
|||
Loading…
Reference in a new issue