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pxa3xx_nand: add new nand chip support
Support samsung 2GbX8 and 32GbX8 nand flash. Support micron 4GbX8 and 4GbX16 nand flash. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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1 changed files with 48 additions and 0 deletions
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@ -226,6 +226,28 @@ static struct pxa3xx_nand_flash samsung512MbX16 = {
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.chip_id = 0x46ec,
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};
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static struct pxa3xx_nand_flash samsung2GbX8 = {
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.timing = &samsung512MbX16_timing,
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.cmdset = &smallpage_cmdset,
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.page_per_block = 64,
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.page_size = 2048,
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.flash_width = 8,
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.dfc_width = 8,
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.num_blocks = 2048,
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.chip_id = 0xdaec,
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};
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static struct pxa3xx_nand_flash samsung32GbX8 = {
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.timing = &samsung512MbX16_timing,
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.cmdset = &smallpage_cmdset,
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.page_per_block = 128,
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.page_size = 4096,
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.flash_width = 8,
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.dfc_width = 8,
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.num_blocks = 8192,
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.chip_id = 0xd7ec,
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};
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static struct pxa3xx_nand_timing micron_timing = {
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.tCH = 10,
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.tCS = 25,
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@ -260,6 +282,28 @@ static struct pxa3xx_nand_flash micron1GbX16 = {
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.chip_id = 0xb12c,
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};
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static struct pxa3xx_nand_flash micron4GbX8 = {
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.timing = µn_timing,
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.cmdset = &largepage_cmdset,
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.page_per_block = 64,
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.page_size = 2048,
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.flash_width = 8,
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.dfc_width = 8,
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.num_blocks = 4096,
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.chip_id = 0xdc2c,
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};
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static struct pxa3xx_nand_flash micron4GbX16 = {
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.timing = µn_timing,
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.cmdset = &largepage_cmdset,
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.page_per_block = 64,
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.page_size = 2048,
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.flash_width = 16,
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.dfc_width = 16,
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.num_blocks = 4096,
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.chip_id = 0xcc2c,
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};
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static struct pxa3xx_nand_timing stm2GbX16_timing = {
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.tCH = 10,
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.tCS = 35,
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@ -285,8 +329,12 @@ static struct pxa3xx_nand_flash stm2GbX16 = {
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static struct pxa3xx_nand_flash *builtin_flash_types[] = {
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&samsung512MbX16,
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&samsung2GbX8,
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&samsung32GbX8,
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µn1GbX8,
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µn1GbX16,
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µn4GbX8,
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µn4GbX16,
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&stm2GbX16,
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};
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#endif /* CONFIG_MTD_NAND_PXA3xx_BUILTIN */
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