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https://github.com/adulau/aha.git
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sh: Fix up extended mode TLB for SH-X2+ cores.
The extended mode TLB requires both 64-bit PTEs and a 64-bit pgprot, correspondingly, the PGD also has to be 64-bits, so fix that up. The kernel and user permission bits really are decoupled in early cuts of the silicon, which means that we also have to set corresponding kernel permissions on user pages or we end up with user pages that the kernel simply can't touch (!). Finally, with those things corrected, really enable MMUCR.ME and correct the PTEA value (this simply needs to be the upper 32-bits of the PTE, with the size and protection bit encoding). Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
parent
db2504966c
commit
d04a0f79f5
4 changed files with 89 additions and 73 deletions
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@ -4,27 +4,14 @@
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* SH-4 specific TLB operations
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*
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* Copyright (C) 1999 Niibe Yutaka
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* Copyright (C) 2002 Paul Mundt
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* Copyright (C) 2002 - 2007 Paul Mundt
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*
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* Released under the terms of the GNU GPL v2.0.
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*/
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <linux/ptrace.h>
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#include <linux/mman.h>
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#include <linux/mm.h>
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#include <linux/smp.h>
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#include <linux/smp_lock.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#include <asm/uaccess.h>
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#include <asm/pgalloc.h>
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#include <asm/mmu_context.h>
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#include <asm/cacheflush.h>
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@ -62,12 +49,22 @@ void update_mmu_cache(struct vm_area_struct * vma,
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vpn = (address & MMU_VPN_MASK) | get_asid();
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ctrl_outl(vpn, MMU_PTEH);
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pteval = pte_val(pte);
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pteval = pte.pte_low;
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/* Set PTEA register */
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#ifdef CONFIG_X2TLB
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/*
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* For the extended mode TLB this is trivial, only the ESZ and
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* EPR bits need to be written out to PTEA, with the remainder of
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* the protection bits (with the exception of the compat-mode SZ
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* and PR bits, which are cleared) being written out in PTEL.
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*/
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ctrl_outl(pte.pte_high, MMU_PTEA);
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#else
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if (cpu_data->flags & CPU_HAS_PTEA)
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/* TODO: make this look less hacky */
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ctrl_outl(((pteval >> 28) & 0xe) | (pteval & 0x1), MMU_PTEA);
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#endif
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/* Set PTEL register */
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pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
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@ -98,4 +95,3 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page)
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ctrl_outl(data, addr);
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back_to_P1();
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}
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@ -22,13 +22,21 @@
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#define MMU_UTLB_ADDRESS_ARRAY 0xF6000000
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#define MMU_PAGE_ASSOC_BIT 0x80
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#define MMU_NTLB_ENTRIES 64 /* for 7750 */
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#ifdef CONFIG_SH_STORE_QUEUES
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#define MMU_CONTROL_INIT 0x05 /* SQMD=0, SV=0, TI=1, AT=1 */
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#ifdef CONFIG_X2TLB
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#define MMUCR_ME (1 << 7)
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#else
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#define MMU_CONTROL_INIT 0x205 /* SQMD=1, SV=0, TI=1, AT=1 */
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#define MMUCR_ME (0)
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#endif
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#ifdef CONFIG_SH_STORE_QUEUES
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#define MMUCR_SQMD (1 << 9)
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#else
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#define MMUCR_SQMD (0)
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#endif
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#define MMU_NTLB_ENTRIES 64
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#define MMU_CONTROL_INIT (0x05|MMUCR_SQMD|MMUCR_ME)
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#define MMU_ITLB_DATA_ARRAY 0xF3000000
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#define MMU_UTLB_DATA_ARRAY 0xF7000000
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@ -88,6 +88,7 @@ extern void __copy_user_page(void *to, void *from, void *orig_to);
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#ifdef CONFIG_X2TLB
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typedef struct { unsigned long pte_low, pte_high; } pte_t;
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typedef struct { unsigned long long pgprot; } pgprot_t;
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typedef struct { unsigned long long pgd; } pgd_t;
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#define pte_val(x) \
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((x).pte_low | ((unsigned long long)(x).pte_high << 32))
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#define __pte(x) \
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@ -95,12 +96,11 @@ typedef struct { unsigned long long pgprot; } pgprot_t;
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#else
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typedef struct { unsigned long pte_low; } pte_t;
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typedef struct { unsigned long pgprot; } pgprot_t;
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typedef struct { unsigned long pgd; } pgd_t;
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#define pte_val(x) ((x).pte_low)
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#define __pte(x) ((pte_t) { (x) } )
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#endif
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typedef struct { unsigned long pgd; } pgd_t;
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#define pgd_val(x) ((x).pgd)
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#define pgprot_val(x) ((x).pgprot)
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@ -42,13 +42,12 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
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/* PGD bits */
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#define PGDIR_SHIFT (PTE_SHIFT + PTE_BITS)
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#define PGDIR_BITS (32 - PGDIR_SHIFT)
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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/* Entries per level */
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#define PTRS_PER_PTE (PAGE_SIZE / (1 << PTE_MAGNITUDE))
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#define PTRS_PER_PGD (PAGE_SIZE / 4)
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#define PTRS_PER_PGD (PAGE_SIZE / sizeof(pgd_t))
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#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
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#define FIRST_USER_ADDRESS 0
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@ -100,17 +99,18 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
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#define _PAGE_HW_SHARED 0x002 /* SH-bit : shared among processes */
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#define _PAGE_DIRTY 0x004 /* D-bit : page changed */
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#define _PAGE_CACHABLE 0x008 /* C-bit : cachable */
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#ifndef CONFIG_X2TLB
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#define _PAGE_SZ0 0x010 /* SZ0-bit : Size of page */
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#define _PAGE_RW 0x020 /* PR0-bit : write access allowed */
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#define _PAGE_USER 0x040 /* PR1-bit : user space access allowed*/
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#define _PAGE_SZ1 0x080 /* SZ1-bit : Size of page (on SH-4) */
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#endif
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#define _PAGE_PRESENT 0x100 /* V-bit : page is valid */
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#define _PAGE_PROTNONE 0x200 /* software: if not present */
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#define _PAGE_ACCESSED 0x400 /* software: page referenced */
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#define _PAGE_FILE _PAGE_WT /* software: pagecache or swap? */
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#define _PAGE_SZ_MASK (_PAGE_SZ0 | _PAGE_SZ1)
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#define _PAGE_PR_MASK (_PAGE_RW | _PAGE_USER)
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/* Extended mode bits */
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#define _PAGE_EXT_ESZ0 0x0010 /* ESZ0-bit: Size of page */
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#define _PAGE_EXT_ESZ1 0x0020 /* ESZ1-bit: Size of page */
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@ -126,11 +126,7 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
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#define _PAGE_EXT_KERN_READ 0x2000 /* EPR5-bit: Kernel space readable */
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/* Wrapper for extended mode pgprot twiddling */
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#ifdef CONFIG_X2TLB
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#define _PAGE_EXT(x) ((unsigned long long)(x) << 32)
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#else
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# define _PAGE_EXT(x) (0)
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#endif
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/* software: moves to PTEA.TC (Timing Control) */
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#define _PAGE_PCC_AREA5 0x00000000 /* use BSC registers for area5 */
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@ -146,10 +142,14 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
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#define _PAGE_PCC_ATR16 0x60000001 /* Attribute Memory space, 6 bit bus */
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/* Mask which drops unused bits from the PTEL value */
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#ifdef CONFIG_CPU_SH3
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#if defined(CONFIG_CPU_SH3)
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#define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED| \
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_PAGE_FILE | _PAGE_SZ1 | \
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_PAGE_HW_SHARED)
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#elif defined(CONFIG_X2TLB)
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/* Get rid of the legacy PR/SZ bits when using extended mode */
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#define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED | \
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_PAGE_FILE | _PAGE_PR_MASK | _PAGE_SZ_MASK)
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#else
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#define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED | _PAGE_FILE)
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#endif
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@ -212,27 +212,36 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
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#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
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_PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
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_PAGE_EXT(_PAGE_EXT_USER_READ | \
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_PAGE_EXT(_PAGE_EXT_KERN_READ | \
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_PAGE_EXT_KERN_WRITE | \
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_PAGE_EXT_USER_READ | \
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_PAGE_EXT_USER_WRITE))
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#define PAGE_EXECREAD __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
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_PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
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_PAGE_EXT(_PAGE_EXT_USER_EXEC | \
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_PAGE_EXT(_PAGE_EXT_KERN_EXEC | \
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_PAGE_EXT_KERN_READ | \
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_PAGE_EXT_USER_EXEC | \
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_PAGE_EXT_USER_READ))
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#define PAGE_COPY PAGE_EXECREAD
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#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
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_PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
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_PAGE_EXT(_PAGE_EXT_USER_READ))
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_PAGE_EXT(_PAGE_EXT_KERN_READ | \
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_PAGE_EXT_USER_READ))
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#define PAGE_WRITEONLY __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
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_PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
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_PAGE_EXT(_PAGE_EXT_USER_WRITE))
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_PAGE_EXT(_PAGE_EXT_KERN_WRITE | \
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_PAGE_EXT_USER_WRITE))
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#define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
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_PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
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_PAGE_EXT(_PAGE_EXT_USER_WRITE | \
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_PAGE_EXT(_PAGE_EXT_KERN_WRITE | \
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_PAGE_EXT_KERN_READ | \
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_PAGE_EXT_KERN_EXEC | \
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_PAGE_EXT_USER_WRITE | \
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_PAGE_EXT_USER_READ | \
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_PAGE_EXT_USER_EXEC))
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@ -373,11 +382,15 @@ static inline void set_pte(pte_t *ptep, pte_t pte)
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#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
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#define pte_pfn(x) ((unsigned long)(((x).pte_low >> PAGE_SHIFT)))
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#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
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#define pfn_pmd(pfn, prot) __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
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#define pfn_pte(pfn, prot) \
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__pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
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#define pfn_pmd(pfn, prot) \
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__pmd(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
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#define pte_none(x) (!pte_val(x))
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#define pte_present(x) (pte_val(x) & (_PAGE_PRESENT | _PAGE_PROTNONE))
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#define pte_present(x) ((x).pte_low & (_PAGE_PRESENT | _PAGE_PROTNONE))
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#define pte_clear(mm,addr,xp) do { set_pte_at(mm, addr, xp, __pte(0)); } while (0)
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#define pmd_none(x) (!pmd_val(x))
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@ -392,15 +405,15 @@ static inline void set_pte(pte_t *ptep, pte_t pte)
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* The following only work if pte_present() is true.
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* Undefined behaviour if not..
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*/
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#define pte_not_present(pte) (!(pte_val(pte) & _PAGE_PRESENT))
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#define pte_dirty(pte) (pte_val(pte) & _PAGE_DIRTY)
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#define pte_young(pte) (pte_val(pte) & _PAGE_ACCESSED)
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#define pte_file(pte) (pte_val(pte) & _PAGE_FILE)
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#define pte_not_present(pte) (!((pte).pte_low & _PAGE_PRESENT))
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#define pte_dirty(pte) ((pte).pte_low & _PAGE_DIRTY)
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#define pte_young(pte) ((pte).pte_low & _PAGE_ACCESSED)
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#define pte_file(pte) ((pte).pte_low & _PAGE_FILE)
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#ifdef CONFIG_X2TLB
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#define pte_write(pte) ((pte).pte_high & _PAGE_EXT_USER_WRITE)
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#else
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#define pte_write(pte) (pte_val(pte) & _PAGE_RW)
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#define pte_write(pte) ((pte).pte_low & _PAGE_RW)
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#endif
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#define PTE_BIT_FUNC(h,fn,op) \
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@ -429,17 +442,10 @@ PTE_BIT_FUNC(low, mkyoung, |= _PAGE_ACCESSED);
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/*
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* Macro and implementation to make a page protection as uncachable.
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*/
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#define pgprot_noncached pgprot_noncached
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#define pgprot_writecombine(prot) \
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__pgprot(pgprot_val(prot) & ~_PAGE_CACHABLE)
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static inline pgprot_t pgprot_noncached(pgprot_t _prot)
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{
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unsigned long prot = pgprot_val(_prot);
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prot &= ~_PAGE_CACHABLE;
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return __pgprot(prot);
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}
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#define pgprot_writecombine(prot) __pgprot(pgprot_val(prot) & ~_PAGE_CACHABLE)
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#define pgprot_noncached pgprot_writecombine
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/*
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* Conversion functions: convert a page and protection to a page entry,
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@ -451,12 +457,17 @@ static inline pgprot_t pgprot_noncached(pgprot_t _prot)
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static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
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{
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set_pte(&pte, __pte((pte_val(pte) & _PAGE_CHG_MASK) |
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pgprot_val(newprot)));
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pte.pte_low &= _PAGE_CHG_MASK;
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pte.pte_low |= pgprot_val(newprot);
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#ifdef CONFIG_X2TLB
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pte.pte_high |= pgprot_val(newprot) >> 32;
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#endif
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return pte;
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}
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#define pmd_page_vaddr(pmd) pmd_val(pmd)
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#define pmd_page_vaddr(pmd) ((unsigned long)pmd_val(pmd))
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#define pmd_page(pmd) (virt_to_page(pmd_val(pmd)))
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/* to find an entry in a page-table-directory. */
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@ -467,12 +478,12 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
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#define pgd_offset_k(address) pgd_offset(&init_mm, address)
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/* Find an entry in the third-level page table.. */
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#define pte_index(address) \
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((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
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#define pte_index(address) ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
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#define pte_offset_kernel(dir, address) \
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((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(address))
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#define pte_offset_map(dir, address) pte_offset_kernel(dir, address)
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#define pte_offset_map_nested(dir, address) pte_offset_kernel(dir, address)
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#define pte_unmap(pte) do { } while (0)
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#define pte_unmap_nested(pte) do { } while (0)
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@ -480,13 +491,14 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
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#define pte_ERROR(e) \
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printk("%s:%d: bad pte %p(%08lx%08lx).\n", __FILE__, __LINE__, \
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&(e), (e).pte_high, (e).pte_low)
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#define pgd_ERROR(e) \
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printk("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e))
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#else
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#define pte_ERROR(e) \
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printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
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#endif
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#define pgd_ERROR(e) \
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printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
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#endif
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struct vm_area_struct;
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extern void update_mmu_cache(struct vm_area_struct * vma,
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