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cs5535: drop the Geode-specific MFGPT/GPIO code
With generic modular drivers handling all of this stuff, the geode-specific code can go away. The cs5535-gpio, cs5535-mfgpt, and cs5535-clockevt drivers now handle this. Signed-off-by: Andres Salomon <dilinger@collabora.co.uk> Cc: Jordan Crouse <jordan@cosmicpenguin.net> Cc: Ingo Molnar <mingo@elte.hu> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: john stultz <johnstul@us.ibm.com> Cc: Chris Ball <cjb@laptop.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Andres Salomon
Linus Torvalds
parent
f3a57a60d3
commit
c95d1e53ed
7 changed files with 2 additions and 714 deletions
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@ -2012,16 +2012,6 @@ config SCx200HR_TIMER
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processor goes idle (as is done by the scheduler). The
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other workaround is idle=poll boot option.
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config GEODE_MFGPT_TIMER
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def_bool y
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prompt "Geode Multi-Function General Purpose Timer (MFGPT) events"
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depends on MGEODE_LX && GENERIC_TIME && GENERIC_CLOCKEVENTS
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---help---
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This driver provides a clock event source based on the MFGPT
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timer(s) in the CS5535 and CS5536 companion chip for the geode.
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MFGPTs have a better resolution and max interval than the
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generic PIT, and are suitable for use as high-res timers.
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config OLPC
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bool "One Laptop Per Child support"
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select GPIOLIB
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@ -14,98 +14,6 @@
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#include <linux/io.h>
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#include <linux/cs5535.h>
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/* Generic southbridge functions */
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#define GEODE_DEV_PMS 0
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#define GEODE_DEV_ACPI 1
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#define GEODE_DEV_GPIO 2
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#define GEODE_DEV_MFGPT 3
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extern int geode_get_dev_base(unsigned int dev);
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/* Useful macros */
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#define geode_pms_base() geode_get_dev_base(GEODE_DEV_PMS)
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#define geode_acpi_base() geode_get_dev_base(GEODE_DEV_ACPI)
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#define geode_gpio_base() geode_get_dev_base(GEODE_DEV_GPIO)
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#define geode_mfgpt_base() geode_get_dev_base(GEODE_DEV_MFGPT)
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/* MSRS */
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#define MSR_LBAR_SMB 0x5140000B
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#define MSR_LBAR_GPIO 0x5140000C
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#define MSR_LBAR_MFGPT 0x5140000D
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#define MSR_LBAR_ACPI 0x5140000E
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#define MSR_LBAR_PMS 0x5140000F
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/* Resource Sizes */
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#define LBAR_GPIO_SIZE 0xFF
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#define LBAR_MFGPT_SIZE 0x40
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#define LBAR_ACPI_SIZE 0x40
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#define LBAR_PMS_SIZE 0x80
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/* ACPI registers (PMS block) */
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/*
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* PM1_EN is only valid when VSA is enabled for 16 bit reads.
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* When VSA is not enabled, *always* read both PM1_STS and PM1_EN
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* with a 32 bit read at offset 0x0
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*/
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#define PM1_STS 0x00
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#define PM1_EN 0x02
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#define PM1_CNT 0x08
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#define PM2_CNT 0x0C
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#define PM_TMR 0x10
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#define PM_GPE0_STS 0x18
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#define PM_GPE0_EN 0x1C
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/* PMC registers (PMS block) */
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#define PM_SSD 0x00
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#define PM_SCXA 0x04
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#define PM_SCYA 0x08
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#define PM_OUT_SLPCTL 0x0C
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#define PM_SCLK 0x10
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#define PM_SED 0x1
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#define PM_SCXD 0x18
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#define PM_SCYD 0x1C
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#define PM_IN_SLPCTL 0x20
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#define PM_WKD 0x30
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#define PM_WKXD 0x34
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#define PM_RD 0x38
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#define PM_WKXA 0x3C
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#define PM_FSD 0x40
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#define PM_TSD 0x44
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#define PM_PSD 0x48
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#define PM_NWKD 0x4C
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#define PM_AWKD 0x50
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#define PM_SSC 0x54
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static inline u32 geode_gpio(unsigned int nr)
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{
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BUG_ON(nr > 28);
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return 1 << nr;
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}
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extern void geode_gpio_set(u32, unsigned int);
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extern void geode_gpio_clear(u32, unsigned int);
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extern int geode_gpio_isset(u32, unsigned int);
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extern void geode_gpio_setup_event(unsigned int, int, int);
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extern void geode_gpio_set_irq(unsigned int, unsigned int);
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static inline void geode_gpio_event_irq(unsigned int gpio, int pair)
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{
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geode_gpio_setup_event(gpio, pair, 0);
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}
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static inline void geode_gpio_event_pme(unsigned int gpio, int pair)
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{
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geode_gpio_setup_event(gpio, pair, 1);
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}
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/* Specific geode tests */
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static inline int is_geode_gx(void)
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{
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return ((boot_cpu_data.x86_vendor == X86_VENDOR_NSC) &&
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@ -125,29 +33,4 @@ static inline int is_geode(void)
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return (is_geode_gx() || is_geode_lx());
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}
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static inline void geode_mfgpt_write(int timer, u16 reg, u16 value)
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{
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u32 base = geode_get_dev_base(GEODE_DEV_MFGPT);
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outw(value, base + reg + (timer * 8));
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}
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static inline u16 geode_mfgpt_read(int timer, u16 reg)
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{
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u32 base = geode_get_dev_base(GEODE_DEV_MFGPT);
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return inw(base + reg + (timer * 8));
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}
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extern int geode_mfgpt_toggle_event(int timer, int cmp, int event, int enable);
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extern int geode_mfgpt_set_irq(int timer, int cmp, int *irq, int enable);
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extern int geode_mfgpt_alloc_timer(int timer, int domain);
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#define geode_mfgpt_setup_irq(t, c, i) geode_mfgpt_set_irq((t), (c), (i), 1)
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#define geode_mfgpt_release_irq(t, c, i) geode_mfgpt_set_irq((t), (c), (i), 0)
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#ifdef CONFIG_GEODE_MFGPT_TIMER
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extern int __init mfgpt_timer_setup(void);
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#else
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static inline int mfgpt_timer_setup(void) { return 0; }
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#endif
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#endif /* _ASM_X86_GEODE_H */
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@ -89,7 +89,6 @@ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
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obj-$(CONFIG_HPET_TIMER) += hpet.o
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obj-$(CONFIG_K8_NB) += k8.o
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obj-$(CONFIG_MGEODE_LX) += geode_32.o mfgpt_32.o
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obj-$(CONFIG_DEBUG_RODATA_TEST) += test_rodata.o
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obj-$(CONFIG_DEBUG_NX_TEST) += test_nx.o
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@ -1,174 +0,0 @@
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/*
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* AMD Geode southbridge support code
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* Copyright (C) 2006, Advanced Micro Devices, Inc.
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* Copyright (C) 2007, Andres Salomon <dilinger@debian.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of version 2 of the GNU General Public License
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* as published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <asm/msr.h>
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#include <asm/geode.h>
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static struct {
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char *name;
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u32 msr;
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int size;
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u32 base;
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} lbars[] = {
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{ "geode-pms", MSR_LBAR_PMS, LBAR_PMS_SIZE, 0 },
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{ "geode-acpi", MSR_LBAR_ACPI, LBAR_ACPI_SIZE, 0 },
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{ "geode-gpio", MSR_LBAR_GPIO, LBAR_GPIO_SIZE, 0 },
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{ "geode-mfgpt", MSR_LBAR_MFGPT, LBAR_MFGPT_SIZE, 0 }
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};
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static void __init init_lbars(void)
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{
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u32 lo, hi;
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int i;
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for (i = 0; i < ARRAY_SIZE(lbars); i++) {
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rdmsr(lbars[i].msr, lo, hi);
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if (hi & 0x01)
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lbars[i].base = lo & 0x0000ffff;
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if (lbars[i].base == 0)
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printk(KERN_ERR "geode: Couldn't initialize '%s'\n",
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lbars[i].name);
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}
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}
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int geode_get_dev_base(unsigned int dev)
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{
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BUG_ON(dev >= ARRAY_SIZE(lbars));
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return lbars[dev].base;
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}
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EXPORT_SYMBOL_GPL(geode_get_dev_base);
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/* === GPIO API === */
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void geode_gpio_set(u32 gpio, unsigned int reg)
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{
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u32 base = geode_get_dev_base(GEODE_DEV_GPIO);
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if (!base)
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return;
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/* low bank register */
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if (gpio & 0xFFFF)
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outl(gpio & 0xFFFF, base + reg);
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/* high bank register */
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gpio >>= 16;
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if (gpio)
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outl(gpio, base + 0x80 + reg);
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}
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EXPORT_SYMBOL_GPL(geode_gpio_set);
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void geode_gpio_clear(u32 gpio, unsigned int reg)
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{
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u32 base = geode_get_dev_base(GEODE_DEV_GPIO);
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if (!base)
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return;
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/* low bank register */
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if (gpio & 0xFFFF)
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outl((gpio & 0xFFFF) << 16, base + reg);
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/* high bank register */
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gpio &= (0xFFFF << 16);
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if (gpio)
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outl(gpio, base + 0x80 + reg);
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}
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EXPORT_SYMBOL_GPL(geode_gpio_clear);
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int geode_gpio_isset(u32 gpio, unsigned int reg)
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{
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u32 base = geode_get_dev_base(GEODE_DEV_GPIO);
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u32 val;
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if (!base)
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return 0;
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/* low bank register */
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if (gpio & 0xFFFF) {
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val = inl(base + reg) & (gpio & 0xFFFF);
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if ((gpio & 0xFFFF) == val)
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return 1;
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}
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/* high bank register */
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gpio >>= 16;
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if (gpio) {
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val = inl(base + 0x80 + reg) & gpio;
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if (gpio == val)
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return 1;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(geode_gpio_isset);
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void geode_gpio_set_irq(unsigned int group, unsigned int irq)
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{
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u32 lo, hi;
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if (group > 7 || irq > 15)
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return;
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rdmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
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lo &= ~(0xF << (group * 4));
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lo |= (irq & 0xF) << (group * 4);
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wrmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
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}
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EXPORT_SYMBOL_GPL(geode_gpio_set_irq);
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void geode_gpio_setup_event(unsigned int gpio, int pair, int pme)
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{
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u32 base = geode_get_dev_base(GEODE_DEV_GPIO);
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u32 offset, shift, val;
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if (gpio >= 24)
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offset = GPIO_MAP_W;
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else if (gpio >= 16)
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offset = GPIO_MAP_Z;
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else if (gpio >= 8)
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offset = GPIO_MAP_Y;
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else
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offset = GPIO_MAP_X;
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shift = (gpio % 8) * 4;
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val = inl(base + offset);
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/* Clear whatever was there before */
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val &= ~(0xF << shift);
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/* And set the new value */
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val |= ((pair & 7) << shift);
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/* Set the PME bit if this is a PME event */
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if (pme)
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val |= (1 << (shift + 3));
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outl(val, base + offset);
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}
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EXPORT_SYMBOL_GPL(geode_gpio_setup_event);
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static int __init geode_southbridge_init(void)
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{
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if (!is_geode())
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return -ENODEV;
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init_lbars();
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(void) mfgpt_timer_setup();
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return 0;
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}
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postcore_initcall(geode_southbridge_init);
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@ -1,410 +0,0 @@
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/*
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* Driver/API for AMD Geode Multi-Function General Purpose Timers (MFGPT)
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*
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* Copyright (C) 2006, Advanced Micro Devices, Inc.
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* Copyright (C) 2007, Andres Salomon <dilinger@debian.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of version 2 of the GNU General Public License
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* as published by the Free Software Foundation.
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*
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* The MFGPTs are documented in AMD Geode CS5536 Companion Device Data Book.
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*/
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/*
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* We are using the 32.768kHz input clock - it's the only one that has the
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* ranges we find desirable. The following table lists the suitable
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* divisors and the associated Hz, minimum interval and the maximum interval:
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*
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* Divisor Hz Min Delta (s) Max Delta (s)
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* 1 32768 .00048828125 2.000
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* 2 16384 .0009765625 4.000
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* 4 8192 .001953125 8.000
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* 8 4096 .00390625 16.000
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* 16 2048 .0078125 32.000
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* 32 1024 .015625 64.000
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* 64 512 .03125 128.000
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* 128 256 .0625 256.000
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* 256 128 .125 512.000
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <asm/geode.h>
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#define MFGPT_DEFAULT_IRQ 7
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static struct mfgpt_timer_t {
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unsigned int avail:1;
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} mfgpt_timers[MFGPT_MAX_TIMERS];
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/* Selected from the table above */
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#define MFGPT_DIVISOR 16
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#define MFGPT_SCALE 4 /* divisor = 2^(scale) */
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#define MFGPT_HZ (32768 / MFGPT_DIVISOR)
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#define MFGPT_PERIODIC (MFGPT_HZ / HZ)
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/* Allow for disabling of MFGPTs */
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static int disable;
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static int __init mfgpt_disable(char *s)
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{
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disable = 1;
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return 1;
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}
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__setup("nomfgpt", mfgpt_disable);
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/* Reset the MFGPT timers. This is required by some broken BIOSes which already
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* do the same and leave the system in an unstable state. TinyBIOS 0.98 is
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* affected at least (0.99 is OK with MFGPT workaround left to off).
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*/
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static int __init mfgpt_fix(char *s)
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{
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u32 val, dummy;
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/* The following udocumented bit resets the MFGPT timers */
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val = 0xFF; dummy = 0;
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wrmsr(MSR_MFGPT_SETUP, val, dummy);
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return 1;
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}
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__setup("mfgptfix", mfgpt_fix);
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/*
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* Check whether any MFGPTs are available for the kernel to use. In most
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* cases, firmware that uses AMD's VSA code will claim all timers during
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* bootup; we certainly don't want to take them if they're already in use.
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* In other cases (such as with VSAless OpenFirmware), the system firmware
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* leaves timers available for us to use.
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*/
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static int timers = -1;
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static void geode_mfgpt_detect(void)
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{
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int i;
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u16 val;
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timers = 0;
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if (disable) {
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printk(KERN_INFO "geode-mfgpt: MFGPT support is disabled\n");
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goto done;
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}
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if (!geode_get_dev_base(GEODE_DEV_MFGPT)) {
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printk(KERN_INFO "geode-mfgpt: MFGPT LBAR is not set up\n");
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goto done;
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}
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for (i = 0; i < MFGPT_MAX_TIMERS; i++) {
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val = geode_mfgpt_read(i, MFGPT_REG_SETUP);
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if (!(val & MFGPT_SETUP_SETUP)) {
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mfgpt_timers[i].avail = 1;
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timers++;
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}
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}
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done:
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printk(KERN_INFO "geode-mfgpt: %d MFGPT timers available.\n", timers);
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}
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int geode_mfgpt_toggle_event(int timer, int cmp, int event, int enable)
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{
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u32 msr, mask, value, dummy;
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int shift = (cmp == MFGPT_CMP1) ? 0 : 8;
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if (timer < 0 || timer >= MFGPT_MAX_TIMERS)
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return -EIO;
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/*
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* The register maps for these are described in sections 6.17.1.x of
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* the AMD Geode CS5536 Companion Device Data Book.
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*/
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switch (event) {
|
||||
case MFGPT_EVENT_RESET:
|
||||
/*
|
||||
* XXX: According to the docs, we cannot reset timers above
|
||||
* 6; that is, resets for 7 and 8 will be ignored. Is this
|
||||
* a problem? -dilinger
|
||||
*/
|
||||
msr = MSR_MFGPT_NR;
|
||||
mask = 1 << (timer + 24);
|
||||
break;
|
||||
|
||||
case MFGPT_EVENT_NMI:
|
||||
msr = MSR_MFGPT_NR;
|
||||
mask = 1 << (timer + shift);
|
||||
break;
|
||||
|
||||
case MFGPT_EVENT_IRQ:
|
||||
msr = MSR_MFGPT_IRQ;
|
||||
mask = 1 << (timer + shift);
|
||||
break;
|
||||
|
||||
default:
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
rdmsr(msr, value, dummy);
|
||||
|
||||
if (enable)
|
||||
value |= mask;
|
||||
else
|
||||
value &= ~mask;
|
||||
|
||||
wrmsr(msr, value, dummy);
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(geode_mfgpt_toggle_event);
|
||||
|
||||
int geode_mfgpt_set_irq(int timer, int cmp, int *irq, int enable)
|
||||
{
|
||||
u32 zsel, lpc, dummy;
|
||||
int shift;
|
||||
|
||||
if (timer < 0 || timer >= MFGPT_MAX_TIMERS)
|
||||
return -EIO;
|
||||
|
||||
/*
|
||||
* Unfortunately, MFGPTs come in pairs sharing their IRQ lines. If VSA
|
||||
* is using the same CMP of the timer's Siamese twin, the IRQ is set to
|
||||
* 2, and we mustn't use nor change it.
|
||||
* XXX: Likewise, 2 Linux drivers might clash if the 2nd overwrites the
|
||||
* IRQ of the 1st. This can only happen if forcing an IRQ, calling this
|
||||
* with *irq==0 is safe. Currently there _are_ no 2 drivers.
|
||||
*/
|
||||
rdmsr(MSR_PIC_ZSEL_LOW, zsel, dummy);
|
||||
shift = ((cmp == MFGPT_CMP1 ? 0 : 4) + timer % 4) * 4;
|
||||
if (((zsel >> shift) & 0xF) == 2)
|
||||
return -EIO;
|
||||
|
||||
/* Choose IRQ: if none supplied, keep IRQ already set or use default */
|
||||
if (!*irq)
|
||||
*irq = (zsel >> shift) & 0xF;
|
||||
if (!*irq)
|
||||
*irq = MFGPT_DEFAULT_IRQ;
|
||||
|
||||
/* Can't use IRQ if it's 0 (=disabled), 2, or routed to LPC */
|
||||
if (*irq < 1 || *irq == 2 || *irq > 15)
|
||||
return -EIO;
|
||||
rdmsr(MSR_PIC_IRQM_LPC, lpc, dummy);
|
||||
if (lpc & (1 << *irq))
|
||||
return -EIO;
|
||||
|
||||
/* All chosen and checked - go for it */
|
||||
if (geode_mfgpt_toggle_event(timer, cmp, MFGPT_EVENT_IRQ, enable))
|
||||
return -EIO;
|
||||
if (enable) {
|
||||
zsel = (zsel & ~(0xF << shift)) | (*irq << shift);
|
||||
wrmsr(MSR_PIC_ZSEL_LOW, zsel, dummy);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mfgpt_get(int timer)
|
||||
{
|
||||
mfgpt_timers[timer].avail = 0;
|
||||
printk(KERN_INFO "geode-mfgpt: Registered timer %d\n", timer);
|
||||
return timer;
|
||||
}
|
||||
|
||||
int geode_mfgpt_alloc_timer(int timer, int domain)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (timers == -1) {
|
||||
/* timers haven't been detected yet */
|
||||
geode_mfgpt_detect();
|
||||
}
|
||||
|
||||
if (!timers)
|
||||
return -1;
|
||||
|
||||
if (timer >= MFGPT_MAX_TIMERS)
|
||||
return -1;
|
||||
|
||||
if (timer < 0) {
|
||||
/* Try to find an available timer */
|
||||
for (i = 0; i < MFGPT_MAX_TIMERS; i++) {
|
||||
if (mfgpt_timers[i].avail)
|
||||
return mfgpt_get(i);
|
||||
|
||||
if (i == 5 && domain == MFGPT_DOMAIN_WORKING)
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
/* If they requested a specific timer, try to honor that */
|
||||
if (mfgpt_timers[timer].avail)
|
||||
return mfgpt_get(timer);
|
||||
}
|
||||
|
||||
/* No timers available - too bad */
|
||||
return -1;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(geode_mfgpt_alloc_timer);
|
||||
|
||||
|
||||
#ifdef CONFIG_GEODE_MFGPT_TIMER
|
||||
|
||||
/*
|
||||
* The MFPGT timers on the CS5536 provide us with suitable timers to use
|
||||
* as clock event sources - not as good as a HPET or APIC, but certainly
|
||||
* better than the PIT. This isn't a general purpose MFGPT driver, but
|
||||
* a simplified one designed specifically to act as a clock event source.
|
||||
* For full details about the MFGPT, please consult the CS5536 data sheet.
|
||||
*/
|
||||
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/clockchips.h>
|
||||
|
||||
static unsigned int mfgpt_tick_mode = CLOCK_EVT_MODE_SHUTDOWN;
|
||||
static u16 mfgpt_event_clock;
|
||||
|
||||
static int irq;
|
||||
static int __init mfgpt_setup(char *str)
|
||||
{
|
||||
get_option(&str, &irq);
|
||||
return 1;
|
||||
}
|
||||
__setup("mfgpt_irq=", mfgpt_setup);
|
||||
|
||||
static void mfgpt_disable_timer(u16 clock)
|
||||
{
|
||||
/* avoid races by clearing CMP1 and CMP2 unconditionally */
|
||||
geode_mfgpt_write(clock, MFGPT_REG_SETUP, (u16) ~MFGPT_SETUP_CNTEN |
|
||||
MFGPT_SETUP_CMP1 | MFGPT_SETUP_CMP2);
|
||||
}
|
||||
|
||||
static int mfgpt_next_event(unsigned long, struct clock_event_device *);
|
||||
static void mfgpt_set_mode(enum clock_event_mode, struct clock_event_device *);
|
||||
|
||||
static struct clock_event_device mfgpt_clockevent = {
|
||||
.name = "mfgpt-timer",
|
||||
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
|
||||
.set_mode = mfgpt_set_mode,
|
||||
.set_next_event = mfgpt_next_event,
|
||||
.rating = 250,
|
||||
.cpumask = cpu_all_mask,
|
||||
.shift = 32
|
||||
};
|
||||
|
||||
static void mfgpt_start_timer(u16 delta)
|
||||
{
|
||||
geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_CMP2, (u16) delta);
|
||||
geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_COUNTER, 0);
|
||||
|
||||
geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_SETUP,
|
||||
MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2);
|
||||
}
|
||||
|
||||
static void mfgpt_set_mode(enum clock_event_mode mode,
|
||||
struct clock_event_device *evt)
|
||||
{
|
||||
mfgpt_disable_timer(mfgpt_event_clock);
|
||||
|
||||
if (mode == CLOCK_EVT_MODE_PERIODIC)
|
||||
mfgpt_start_timer(MFGPT_PERIODIC);
|
||||
|
||||
mfgpt_tick_mode = mode;
|
||||
}
|
||||
|
||||
static int mfgpt_next_event(unsigned long delta, struct clock_event_device *evt)
|
||||
{
|
||||
mfgpt_start_timer(delta);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static irqreturn_t mfgpt_tick(int irq, void *dev_id)
|
||||
{
|
||||
u16 val = geode_mfgpt_read(mfgpt_event_clock, MFGPT_REG_SETUP);
|
||||
|
||||
/* See if the interrupt was for us */
|
||||
if (!(val & (MFGPT_SETUP_SETUP | MFGPT_SETUP_CMP2 | MFGPT_SETUP_CMP1)))
|
||||
return IRQ_NONE;
|
||||
|
||||
/* Turn off the clock (and clear the event) */
|
||||
mfgpt_disable_timer(mfgpt_event_clock);
|
||||
|
||||
if (mfgpt_tick_mode == CLOCK_EVT_MODE_SHUTDOWN)
|
||||
return IRQ_HANDLED;
|
||||
|
||||
/* Clear the counter */
|
||||
geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_COUNTER, 0);
|
||||
|
||||
/* Restart the clock in periodic mode */
|
||||
|
||||
if (mfgpt_tick_mode == CLOCK_EVT_MODE_PERIODIC) {
|
||||
geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_SETUP,
|
||||
MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2);
|
||||
}
|
||||
|
||||
mfgpt_clockevent.event_handler(&mfgpt_clockevent);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static struct irqaction mfgptirq = {
|
||||
.handler = mfgpt_tick,
|
||||
.flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER,
|
||||
.name = "mfgpt-timer"
|
||||
};
|
||||
|
||||
int __init mfgpt_timer_setup(void)
|
||||
{
|
||||
int timer, ret;
|
||||
u16 val;
|
||||
|
||||
timer = geode_mfgpt_alloc_timer(MFGPT_TIMER_ANY, MFGPT_DOMAIN_WORKING);
|
||||
if (timer < 0) {
|
||||
printk(KERN_ERR
|
||||
"mfgpt-timer: Could not allocate a MFPGT timer\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
mfgpt_event_clock = timer;
|
||||
|
||||
/* Set up the IRQ on the MFGPT side */
|
||||
if (geode_mfgpt_setup_irq(mfgpt_event_clock, MFGPT_CMP2, &irq)) {
|
||||
printk(KERN_ERR "mfgpt-timer: Could not set up IRQ %d\n", irq);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
/* And register it with the kernel */
|
||||
ret = setup_irq(irq, &mfgptirq);
|
||||
|
||||
if (ret) {
|
||||
printk(KERN_ERR
|
||||
"mfgpt-timer: Unable to set up the interrupt.\n");
|
||||
goto err;
|
||||
}
|
||||
|
||||
/* Set the clock scale and enable the event mode for CMP2 */
|
||||
val = MFGPT_SCALE | (3 << 8);
|
||||
|
||||
geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_SETUP, val);
|
||||
|
||||
/* Set up the clock event */
|
||||
mfgpt_clockevent.mult = div_sc(MFGPT_HZ, NSEC_PER_SEC,
|
||||
mfgpt_clockevent.shift);
|
||||
mfgpt_clockevent.min_delta_ns = clockevent_delta2ns(0xF,
|
||||
&mfgpt_clockevent);
|
||||
mfgpt_clockevent.max_delta_ns = clockevent_delta2ns(0xFFFE,
|
||||
&mfgpt_clockevent);
|
||||
|
||||
printk(KERN_INFO
|
||||
"mfgpt-timer: Registering MFGPT timer %d as a clock event, using IRQ %d\n",
|
||||
timer, irq);
|
||||
clockevents_register_device(&mfgpt_clockevent);
|
||||
|
||||
return 0;
|
||||
|
||||
err:
|
||||
geode_mfgpt_release_irq(mfgpt_event_clock, MFGPT_CMP2, &irq);
|
||||
printk(KERN_ERR
|
||||
"mfgpt-timer: Unable to set up the MFGPT clock source\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -176,7 +176,7 @@ comment "PCI GPIO expanders:"
|
|||
|
||||
config GPIO_CS5535
|
||||
tristate "AMD CS5535/CS5536 GPIO support"
|
||||
depends on PCI && !CS5535_GPIO && !MGEODE_LX
|
||||
depends on PCI && !CS5535_GPIO
|
||||
help
|
||||
The AMD CS5535 and CS5536 southbridges support 28 GPIO pins that
|
||||
can be used for quite a number of things. The CS5535/6 is found on
|
||||
|
|
|
|||
|
|
@ -189,7 +189,7 @@ config SGI_XP
|
|||
|
||||
config CS5535_MFGPT
|
||||
tristate "CS5535/CS5536 Geode Multi-Function General Purpose Timer (MFGPT) support"
|
||||
depends on PCI && !MGEODE_LX
|
||||
depends on PCI
|
||||
depends on X86
|
||||
default n
|
||||
help
|
||||
|
|
|
|||
Loading…
Reference in a new issue