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powerpc/5200: Enable CPU_FTR_NEED_COHERENT for MPC52xx
BestComm, a DMA engine in MPC52xx SoC, requires snooping when
CPU caches are enabled to work properly.
Adding CPU_FTR_NEED_COHERENT fixes NFS problems on MPC52xx machines
introduced by 'powerpc/mm: Fix handling of _PAGE_COHERENT in BAT setup
code' (sha1: 4c456a67f5
).
Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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1 changed files with 3 additions and 1 deletions
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@ -241,9 +241,11 @@ extern const char *powerpc_base_platform;
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/* We need to mark all pages as being coherent if we're SMP or we have a
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/* We need to mark all pages as being coherent if we're SMP or we have a
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* 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
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* 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
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* require it for PCI "streaming/prefetch" to work properly.
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* require it for PCI "streaming/prefetch" to work properly.
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* This is also required by 52xx family.
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*/
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*/
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#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
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#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
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|| defined(CONFIG_PPC_83xx) || defined(CONFIG_8260)
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|| defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
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|| defined(CONFIG_PPC_MPC52xx)
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#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
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#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
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#else
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#else
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#define CPU_FTR_COMMON 0
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#define CPU_FTR_COMMON 0
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