mirror of
https://github.com/adulau/aha.git
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Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6
* master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6: [SPARC] uctrl: Check request_irq() return value. [SPARC64]: Update defconfig. [SPARC64] bbc_i2c: Fix kenvctrld eating %100 cpu. [SPARC64]: Fix arch_teardown_msi_irq(). [SPARC64]: virt_irq_free only needed when CONFIG_PCI_MSI [SPARC]: Remove the broken SUN_AURORA driver.
This commit is contained in:
Linus Torvalds
commit
c90c69a508
11 changed files with 42 additions and 2902 deletions
|
|
@ -65,7 +65,6 @@ CMAGIC 0x0111 user include/linux/a.out.h
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|||
MKISS_DRIVER_MAGIC 0x04bf mkiss_channel drivers/net/mkiss.h
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||||
RISCOM8_MAGIC 0x0907 riscom_port drivers/char/riscom8.h
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||||
SPECIALIX_MAGIC 0x0907 specialix_port drivers/char/specialix_io8.h
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||||
AURORA_MAGIC 0x0A18 Aurora_port drivers/sbus/char/aurora.h
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HDLC_MAGIC 0x239e n_hdlc drivers/char/n_hdlc.c
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APM_BIOS_MAGIC 0x4101 apm_user arch/i386/kernel/apm.c
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CYCLADES_MAGIC 0x4359 cyclades_port include/linux/cyclades.h
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@ -1,7 +1,7 @@
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#
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# Automatically generated make config: don't edit
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# Linux kernel version: 2.6.20
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# Sun Feb 11 23:47:40 2007
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# Linux kernel version: 2.6.21-rc1
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# Mon Feb 26 10:45:21 2007
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#
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CONFIG_SPARC=y
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CONFIG_SPARC64=y
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@ -41,6 +41,7 @@ CONFIG_LOCALVERSION=""
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CONFIG_SWAP=y
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CONFIG_SYSVIPC=y
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# CONFIG_IPC_NS is not set
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CONFIG_SYSVIPC_SYSCTL=y
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CONFIG_POSIX_MQUEUE=y
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# CONFIG_BSD_PROCESS_ACCT is not set
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# CONFIG_TASKSTATS is not set
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@ -322,6 +323,7 @@ CONFIG_CONNECTOR=m
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#
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# Plug and Play support
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#
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# CONFIG_PNPACPI is not set
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#
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# Block devices
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@ -787,6 +789,7 @@ CONFIG_I2C_ALGOBIT=y
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# CONFIG_I2C_NFORCE2 is not set
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# CONFIG_I2C_OCORES is not set
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# CONFIG_I2C_PARPORT_LIGHT is not set
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# CONFIG_I2C_PASEMI is not set
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# CONFIG_I2C_PROSAVAGE is not set
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# CONFIG_I2C_SAVAGE4 is not set
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# CONFIG_I2C_SIS5595 is not set
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@ -833,6 +836,7 @@ CONFIG_HWMON=y
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# CONFIG_SENSORS_ADM1021 is not set
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# CONFIG_SENSORS_ADM1025 is not set
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# CONFIG_SENSORS_ADM1026 is not set
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# CONFIG_SENSORS_ADM1029 is not set
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# CONFIG_SENSORS_ADM1031 is not set
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# CONFIG_SENSORS_ADM9240 is not set
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# CONFIG_SENSORS_ASB100 is not set
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@ -873,6 +877,11 @@ CONFIG_HWMON=y
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# CONFIG_SENSORS_W83627EHF is not set
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# CONFIG_HWMON_DEBUG_CHIP is not set
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#
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# Multifunction device drivers
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#
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# CONFIG_MFD_SM501 is not set
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#
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# Multimedia devices
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#
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@ -887,16 +896,22 @@ CONFIG_HWMON=y
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#
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# Graphics support
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#
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# CONFIG_FIRMWARE_EDID is not set
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# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
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CONFIG_FB=y
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# CONFIG_FIRMWARE_EDID is not set
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CONFIG_FB_DDC=y
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CONFIG_FB_CFB_FILLRECT=y
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CONFIG_FB_CFB_COPYAREA=y
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CONFIG_FB_CFB_IMAGEBLIT=y
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# CONFIG_FB_SVGALIB is not set
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# CONFIG_FB_MACMODES is not set
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# CONFIG_FB_BACKLIGHT is not set
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CONFIG_FB_MODE_HELPERS=y
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CONFIG_FB_TILEBLITTING=y
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#
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# Frambuffer hardware drivers
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#
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# CONFIG_FB_CIRRUS is not set
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# CONFIG_FB_PM2 is not set
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# CONFIG_FB_ASILIANT is not set
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@ -908,9 +923,11 @@ CONFIG_FB_TILEBLITTING=y
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# CONFIG_FB_MATROX is not set
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CONFIG_FB_RADEON=y
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CONFIG_FB_RADEON_I2C=y
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# CONFIG_FB_RADEON_BACKLIGHT is not set
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# CONFIG_FB_RADEON_DEBUG is not set
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# CONFIG_FB_ATY128 is not set
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# CONFIG_FB_ATY is not set
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# CONFIG_FB_S3 is not set
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# CONFIG_FB_SAVAGE is not set
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# CONFIG_FB_SIS is not set
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# CONFIG_FB_NEOMAGIC is not set
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@ -947,7 +964,6 @@ CONFIG_LOGO=y
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# CONFIG_LOGO_LINUX_VGA16 is not set
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# CONFIG_LOGO_LINUX_CLUT224 is not set
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CONFIG_LOGO_SUN_CLUT224=y
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# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
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#
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# Sound
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@ -1192,6 +1208,7 @@ CONFIG_USB_HIDDEV=y
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# CONFIG_USB_RIO500 is not set
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# CONFIG_USB_LEGOTOWER is not set
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# CONFIG_USB_LCD is not set
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# CONFIG_USB_BERRY_CHARGE is not set
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# CONFIG_USB_LED is not set
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# CONFIG_USB_CYPRESS_CY7C63 is not set
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# CONFIG_USB_CYTHERM is not set
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@ -1445,9 +1462,11 @@ CONFIG_MAGIC_SYSRQ=y
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CONFIG_DEBUG_FS=y
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# CONFIG_HEADERS_CHECK is not set
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CONFIG_DEBUG_KERNEL=y
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# CONFIG_DEBUG_SHIRQ is not set
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CONFIG_LOG_BUF_SHIFT=18
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CONFIG_DETECT_SOFTLOCKUP=y
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CONFIG_SCHEDSTATS=y
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# CONFIG_TIMER_STATS is not set
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# CONFIG_DEBUG_SLAB is not set
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# CONFIG_DEBUG_RT_MUTEXES is not set
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# CONFIG_RT_MUTEX_TESTER is not set
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@ -1465,6 +1484,7 @@ CONFIG_DEBUG_BUGVERBOSE=y
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CONFIG_FORCED_INLINING=y
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# CONFIG_RCU_TORTURE_TEST is not set
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# CONFIG_LKDTM is not set
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# CONFIG_FAULT_INJECTION is not set
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# CONFIG_DEBUG_STACK_USAGE is not set
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# CONFIG_DEBUG_DCFLUSH is not set
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# CONFIG_STACK_DEBUG is not set
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@ -109,6 +109,7 @@ static unsigned char virt_irq_alloc(unsigned int real_irq)
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return ent;
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}
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#ifdef CONFIG_PCI_MSI
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static void virt_irq_free(unsigned int virt_irq)
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{
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unsigned int real_irq;
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@ -121,6 +122,7 @@ static void virt_irq_free(unsigned int virt_irq)
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__bucket(real_irq)->virt_irq = 0;
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}
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#endif
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static unsigned int virt_to_real_irq(unsigned char virt_irq)
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{
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@ -668,7 +668,7 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
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void arch_teardown_msi_irq(unsigned int virt_irq)
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{
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struct msi_desc *entry = get_irq_data(virt_irq);
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struct msi_desc *entry = get_irq_msi(virt_irq);
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struct pci_dev *pdev = entry->dev;
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struct pcidev_cookie *pcp = pdev->sysdata;
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struct pci_pbm_info *pbm = pcp->pbm;
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@ -46,13 +46,6 @@ config SUN_VIDEOPIX
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based on the Phillips SAA9051, can handle NTSC and PAL/SECAM and
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SVIDEO signals.
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config SUN_AURORA
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tristate "Aurora Multiboard 1600se (EXPERIMENTAL)"
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depends on EXPERIMENTAL && BROKEN
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help
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The Aurora Multiboard is a multi-port high-speed serial controller.
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If you have one of these, say Y.
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config TADPOLE_TS102_UCTRL
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tristate "Tadpole TS102 Microcontroller support (EXPERIMENTAL)"
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depends on EXPERIMENTAL && SPARC32
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@ -19,7 +19,6 @@ obj-$(CONFIG_SUN_OPENPROMIO) += openprom.o
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obj-$(CONFIG_SUN_MOSTEK_RTC) += rtc.o
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obj-$(CONFIG_SUN_BPP) += bpp.o
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obj-$(CONFIG_SUN_VIDEOPIX) += vfc.o
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obj-$(CONFIG_SUN_AURORA) += aurora.o
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obj-$(CONFIG_TADPOLE_TS102_UCTRL) += uctrl.o
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obj-$(CONFIG_SUN_JSFLASH) += jsflash.o
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obj-$(CONFIG_BBC_I2C) += bbc.o
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File diff suppressed because it is too large
Load diff
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@ -1,276 +0,0 @@
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/* $Id: aurora.h,v 1.6 2001/06/05 12:23:38 davem Exp $
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* linux/drivers/sbus/char/aurora.h -- Aurora multiport driver
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*
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* Copyright (c) 1999 by Oliver Aldulea (oli@bv.ro)
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*
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* This code is based on the RISCom/8 multiport serial driver written
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* by Dmitry Gorodchanin (pgmdsg@ibi.com), based on the Linux serial
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* driver, written by Linus Torvalds, Theodore T'so and others.
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* The Aurora multiport programming info was obtained mainly from the
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* Cirrus Logic CD180 documentation (available on the web), and by
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* doing heavy tests on the board. Many thanks to Eddie C. Dost for the
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* help on the sbus interface.
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*
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||||
* This program is free software; you can redistribute it and/or modify
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||||
* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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||||
* Revision 1.0
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*
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* This is the first public release.
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*
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||||
* This version needs a lot of feedback. This is the version that works
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* with _my_ board. My board is model 1600se, revision '@(#)1600se.fth
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* 1.2 3/28/95 1'. The driver might work with your board, but I do not
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* guarantee it. If you have _any_ type of board, I need to know if the
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* driver works or not, I need to know exactly your board parameters
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* (get them with 'cd /proc/openprom/iommu/sbus/sio16/; ls *; cat *')
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* Also, I need your board revision code, which is written on the board.
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* Send me the output of my driver too (it outputs through klogd).
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*
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* If the driver does not work, you can try enabling the debug options
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* to see what's wrong or what should be done.
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*
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* I'm sorry about the alignment of the code. It was written in a
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* 128x48 environment.
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*
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* I must say that I do not like Aurora Technologies' policy. I asked
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* them to help me do this driver faster, but they ended by something
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* like "don't call us, we'll call you", and I never heard anything
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* from them. They told me "knowing the way the board works, I don't
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* doubt you and others on the net will make the driver."
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* The truth about this board is that it has nothing intelligent on it.
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* If you want to say to somebody what kind of board you have, say that
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* it uses Cirrus Logic processors (CD180). The power of the board is
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* in those two chips. The rest of the board is the interface to the
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* sbus and to the peripherals. Still, they did something smart: they
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* reversed DTR and RTS to make on-board automatic hardware flow
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* control usable.
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||||
* Thanks to Aurora Technologies for wasting my time, nerves and money.
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||||
*/
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||||
|
||||
#ifndef __LINUX_AURORA_H
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||||
#define __LINUX_AURORA_H
|
||||
|
||||
#include <linux/serial.h>
|
||||
#include <linux/serialP.h>
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||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
/* This is the number of boards to support. I've only tested this driver with
|
||||
* one board, so it might not work.
|
||||
*/
|
||||
#define AURORA_NBOARD 1
|
||||
|
||||
/* Useful ? Yes. But you can safely comment the warnings if they annoy you
|
||||
* (let me say that again: the warnings in the code, not this define).
|
||||
*/
|
||||
#define AURORA_PARANOIA_CHECK
|
||||
|
||||
/* Well, after many lost nights, I found that the IRQ for this board is
|
||||
* selected from four built-in values by writing some bits in the
|
||||
* configuration register. This causes a little problem to occur: which
|
||||
* IRQ to select ? Which one is the best for the user ? Well, I finally
|
||||
* decided for the following algorithm: if the "bintr" value is not acceptable
|
||||
* (not within type_1_irq[], then test the "intr" value, if that fails too,
|
||||
* try each value from type_1_irq until succeded. Hope it's ok.
|
||||
* You can safely reorder the irq's.
|
||||
*/
|
||||
#define TYPE_1_IRQS 4
|
||||
unsigned char type_1_irq[TYPE_1_IRQS] = {
|
||||
3, 5, 9, 13
|
||||
};
|
||||
/* I know something about another method of interrupt setting, but not enough.
|
||||
* Also, this is for another type of board, so I first have to learn how to
|
||||
* detect it.
|
||||
#define TYPE_2_IRQS 3
|
||||
unsigned char type_2_irq[TYPE_2_IRQS] = {
|
||||
0, 0, 0 ** could anyone find these for me ? (see AURORA_ALLIRQ below) **
|
||||
};
|
||||
unsigned char type_2_mask[TYPE_2_IRQS] = {
|
||||
32, 64, 128
|
||||
};
|
||||
*/
|
||||
|
||||
/* The following section should only be modified by those who know what
|
||||
* they're doing (or don't, but want to help with some feedback). Modifying
|
||||
* anything raises a _big_ probability for your system to hang, but the
|
||||
* sacrifice worths. (I sacrificed my ext2fs many, many times...)
|
||||
*/
|
||||
|
||||
/* This one tries to dump to console the name of almost every function called,
|
||||
* and many other debugging info.
|
||||
*/
|
||||
#undef AURORA_DEBUG
|
||||
|
||||
/* These are the most dangerous and useful defines. They do printk() during
|
||||
* the interrupt processing routine(s), so if you manage to get "flooded" by
|
||||
* irq's, start thinking about the "Power off/on" button...
|
||||
*/
|
||||
#undef AURORA_INTNORM /* This one enables the "normal" messages, but some
|
||||
* of them cause flood, so I preffered putting
|
||||
* them under a define */
|
||||
#undef AURORA_INT_DEBUG /* This one is really bad. */
|
||||
|
||||
/* Here's something helpful: after n irq's, the board will be disabled. This
|
||||
* prevents irq flooding during debug (no need to think about power
|
||||
* off/on anymore...)
|
||||
*/
|
||||
#define AURORA_FLOODPRO 10
|
||||
|
||||
/* This one helps finding which irq the board calls, in case of a strange/
|
||||
* unsupported board. AURORA_INT_DEBUG should be enabled, because I don't
|
||||
* think /proc/interrupts or any command will be available in case of an irq
|
||||
* flood... "allirq" is the list of all free irq's.
|
||||
*/
|
||||
/*
|
||||
#define AURORA_ALLIRQ 6
|
||||
int allirq[AURORA_ALLIRQ]={
|
||||
2,3,5,7,9,13
|
||||
};
|
||||
*/
|
||||
|
||||
/* These must not be modified. These values are assumed during the code for
|
||||
* performance optimisations.
|
||||
*/
|
||||
#define AURORA_NCD180 2 /* two chips per board */
|
||||
#define AURORA_NPORT 8 /* 8 ports per chip */
|
||||
|
||||
/* several utilities */
|
||||
#define AURORA_BOARD(line) (((line) >> 4) & 0x01)
|
||||
#define AURORA_CD180(line) (((line) >> 3) & 0x01)
|
||||
#define AURORA_PORT(line) ((line) & 15)
|
||||
|
||||
#define AURORA_TNPORTS (AURORA_NBOARD*AURORA_NCD180*AURORA_NPORT)
|
||||
|
||||
/* Ticks per sec. Used for setting receiver timeout and break length */
|
||||
#define AURORA_TPS 4000
|
||||
|
||||
#define AURORA_MAGIC 0x0A18
|
||||
|
||||
/* Yeah, after heavy testing I decided it must be 6.
|
||||
* Sure, You can change it if needed.
|
||||
*/
|
||||
#define AURORA_RXFIFO 6 /* Max. receiver FIFO size (1-8) */
|
||||
|
||||
#define AURORA_RXTH 7
|
||||
|
||||
struct aurora_reg1 {
|
||||
__volatile__ unsigned char r;
|
||||
};
|
||||
|
||||
struct aurora_reg128 {
|
||||
__volatile__ unsigned char r[128];
|
||||
};
|
||||
|
||||
struct aurora_reg4 {
|
||||
__volatile__ unsigned char r[4];
|
||||
};
|
||||
|
||||
struct Aurora_board {
|
||||
unsigned long flags;
|
||||
struct aurora_reg1 * r0; /* This is the board configuration
|
||||
* register (write-only). */
|
||||
struct aurora_reg128 * r[2]; /* These are the registers for the
|
||||
* two chips. */
|
||||
struct aurora_reg4 * r3; /* These are used for hardware-based
|
||||
* acknowledge. Software-based ack is
|
||||
* not supported by CD180. */
|
||||
unsigned int oscfreq; /* The on-board oscillator
|
||||
* frequency, in Hz. */
|
||||
unsigned char irq;
|
||||
#ifdef MODULE
|
||||
signed char count; /* counts the use of the board */
|
||||
#endif
|
||||
/* Values for the dtr_rts swapped mode. */
|
||||
unsigned char DTR;
|
||||
unsigned char RTS;
|
||||
unsigned char MSVDTR;
|
||||
unsigned char MSVRTS;
|
||||
/* Values for hardware acknowledge. */
|
||||
unsigned char ACK_MINT, ACK_TINT, ACK_RINT;
|
||||
};
|
||||
|
||||
/* Board configuration register */
|
||||
#define AURORA_CFG_ENABLE_IO 8
|
||||
#define AURORA_CFG_ENABLE_IRQ 4
|
||||
|
||||
/* Board flags */
|
||||
#define AURORA_BOARD_PRESENT 0x00000001
|
||||
#define AURORA_BOARD_ACTIVE 0x00000002
|
||||
#define AURORA_BOARD_TYPE_2 0x00000004 /* don't know how to
|
||||
* detect this yet */
|
||||
#define AURORA_BOARD_DTR_FLOW_OK 0x00000008
|
||||
|
||||
/* The story goes like this: Cirrus programmed the CD-180 chip to do automatic
|
||||
* hardware flow control, and do it using CTS and DTR. CTS is ok, but, if you
|
||||
* have a modem and the chip drops DTR, then the modem will drop the carrier
|
||||
* (ain't that cute...). Luckily, the guys at Aurora decided to swap DTR and
|
||||
* RTS, which makes the flow control usable. I hope that all the boards made
|
||||
* by Aurora have these two signals swapped. If your's doesn't but you have a
|
||||
* breakout box, you can try to reverse them yourself, then set the following
|
||||
* flag.
|
||||
*/
|
||||
#undef AURORA_FORCE_DTR_FLOW
|
||||
|
||||
/* In fact, a few more words have to be said about hardware flow control.
|
||||
* This driver handles "output" flow control through the on-board facility
|
||||
* CTS Auto Enable. For the "input" flow control there are two cases when
|
||||
* the flow should be controlled. The first case is when the kernel is so
|
||||
* busy that it cannot process IRQ's in time; this flow control can only be
|
||||
* activated by the on-board chip, and if the board has RTS and DTR swapped,
|
||||
* this facility is usable. The second case is when the application is so
|
||||
* busy that it cannot receive bytes from the kernel, and this flow must be
|
||||
* activated by software. This second case is not yet implemented in this
|
||||
* driver. Unfortunately, I estimate that the second case is the one that
|
||||
* occurs the most.
|
||||
*/
|
||||
|
||||
|
||||
struct Aurora_port {
|
||||
int magic;
|
||||
int baud_base;
|
||||
int flags;
|
||||
struct tty_struct * tty;
|
||||
int count;
|
||||
int blocked_open;
|
||||
long event;
|
||||
int timeout;
|
||||
int close_delay;
|
||||
unsigned char * xmit_buf;
|
||||
int custom_divisor;
|
||||
int xmit_head;
|
||||
int xmit_tail;
|
||||
int xmit_cnt;
|
||||
wait_queue_head_t open_wait;
|
||||
wait_queue_head_t close_wait;
|
||||
struct tq_struct tqueue;
|
||||
struct tq_struct tqueue_hangup;
|
||||
short wakeup_chars;
|
||||
short break_length;
|
||||
unsigned short closing_wait;
|
||||
unsigned char mark_mask;
|
||||
unsigned char SRER;
|
||||
unsigned char MSVR;
|
||||
unsigned char COR2;
|
||||
#ifdef AURORA_REPORT_OVERRUN
|
||||
unsigned long overrun;
|
||||
#endif
|
||||
#ifdef AURORA_REPORT_FIFO
|
||||
unsigned long hits[10];
|
||||
#endif
|
||||
};
|
||||
|
||||
#endif
|
||||
#endif /*__LINUX_AURORA_H*/
|
||||
|
||||
|
|
@ -187,19 +187,20 @@ static int wait_for_pin(struct bbc_i2c_bus *bp, u8 *status)
|
|||
bp->waiting = 1;
|
||||
add_wait_queue(&bp->wq, &wait);
|
||||
while (limit-- > 0) {
|
||||
u8 val;
|
||||
unsigned long val;
|
||||
|
||||
set_current_state(TASK_INTERRUPTIBLE);
|
||||
*status = val = readb(bp->i2c_control_regs + 0);
|
||||
if ((val & I2C_PCF_PIN) == 0) {
|
||||
val = wait_event_interruptible_timeout(
|
||||
bp->wq,
|
||||
(((*status = readb(bp->i2c_control_regs + 0))
|
||||
& I2C_PCF_PIN) == 0),
|
||||
msecs_to_jiffies(250));
|
||||
if (val > 0) {
|
||||
ret = 0;
|
||||
break;
|
||||
}
|
||||
msleep_interruptible(250);
|
||||
}
|
||||
remove_wait_queue(&bp->wq, &wait);
|
||||
bp->waiting = 0;
|
||||
current->state = TASK_RUNNING;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -340,7 +341,7 @@ static irqreturn_t bbc_i2c_interrupt(int irq, void *dev_id)
|
|||
*/
|
||||
if (bp->waiting &&
|
||||
!(readb(bp->i2c_control_regs + 0x0) & I2C_PCF_PIN))
|
||||
wake_up(&bp->wq);
|
||||
wake_up_interruptible(&bp->wq);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,240 +0,0 @@
|
|||
|
||||
/* Definitions for Cirrus Logic CL-CD180 8-port async mux chip */
|
||||
#define CD180_NCH 8 /* Total number of channels */
|
||||
#define CD180_TPC 16 /* Ticks per character */
|
||||
#define CD180_NFIFO 8 /* TX FIFO size */
|
||||
|
||||
/* Global registers */
|
||||
#define CD180_GFRCR 0x6b /* Global Firmware Revision Code Register */
|
||||
#define CD180_SRCR 0x66 /* Service Request Configuration Register */
|
||||
#define CD180_PPRH 0x70 /* Prescaler Period Register High */
|
||||
#define CD180_PPRL 0x71 /* Prescaler Period Register Low */
|
||||
#define CD180_MSMR 0x61 /* Modem Service Match Register */
|
||||
#define CD180_TSMR 0x62 /* Transmit Service Match Register */
|
||||
#define CD180_RSMR 0x63 /* Receive Service Match Register */
|
||||
#define CD180_GSVR 0x40 /* Global Service Vector Register */
|
||||
#define CD180_SRSR 0x65 /* Service Request Status Register */
|
||||
#define CD180_GSCR 0x41 /* Global Service Channel Register */
|
||||
#define CD180_CAR 0x64 /* Channel Access Register */
|
||||
|
||||
/* Indexed registers */
|
||||
#define CD180_RDCR 0x07 /* Receive Data Count Register */
|
||||
#define CD180_RDR 0x78 /* Receiver Data Register */
|
||||
#define CD180_RCSR 0x7a /* Receiver Character Status Register */
|
||||
#define CD180_TDR 0x7b /* Transmit Data Register */
|
||||
#define CD180_EOSRR 0x7f /* End of Service Request Register */
|
||||
|
||||
/* Channel Registers */
|
||||
#define CD180_SRER 0x02 /* Service Request Enable Register */
|
||||
#define CD180_CCR 0x01 /* Channel Command Register */
|
||||
#define CD180_COR1 0x03 /* Channel Option Register 1 */
|
||||
#define CD180_COR2 0x04 /* Channel Option Register 2 */
|
||||
#define CD180_COR3 0x05 /* Channel Option Register 3 */
|
||||
#define CD180_CCSR 0x06 /* Channel Control Status Register */
|
||||
#define CD180_RTPR 0x18 /* Receive Timeout Period Register */
|
||||
#define CD180_RBPRH 0x31 /* Receive Bit Rate Period Register High */
|
||||
#define CD180_RBPRL 0x32 /* Receive Bit Rate Period Register Low */
|
||||
#define CD180_TBPRH 0x39 /* Transmit Bit Rate Period Register High */
|
||||
#define CD180_TBPRL 0x3a /* Transmit Bit Rate Period Register Low */
|
||||
#define CD180_SCHR1 0x09 /* Special Character Register 1 */
|
||||
#define CD180_SCHR2 0x0a /* Special Character Register 2 */
|
||||
#define CD180_SCHR3 0x0b /* Special Character Register 3 */
|
||||
#define CD180_SCHR4 0x0c /* Special Character Register 4 */
|
||||
#define CD180_MCR 0x12 /* Modem Change Register */
|
||||
#define CD180_MCOR1 0x10 /* Modem Change Option 1 Register */
|
||||
#define CD180_MCOR2 0x11 /* Modem Change Option 2 Register */
|
||||
#define CD180_MSVR 0x28 /* Modem Signal Value Register */
|
||||
#define CD180_MSVRTS 0x29 /* Modem Signal Value RTS */
|
||||
#define CD180_MSVDTR 0x2a /* Modem Signal Value DTR */
|
||||
|
||||
/* Global Interrupt Vector Register (R/W) */
|
||||
|
||||
#define GSVR_ITMASK 0x07 /* Interrupt type mask */
|
||||
#define GSVR_IT_MDM 0x01 /* Modem Signal Change Interrupt */
|
||||
#define GSVR_IT_TX 0x02 /* Transmit Data Interrupt */
|
||||
#define GSVR_IT_RGD 0x03 /* Receive Good Data Interrupt */
|
||||
#define GSVR_IT_REXC 0x07 /* Receive Exception Interrupt */
|
||||
|
||||
|
||||
/* Global Interrupt Channel Register (R/W) */
|
||||
|
||||
#define GSCR_CHAN 0x1c /* Channel Number Mask */
|
||||
#define GSCR_CHAN_OFF 2 /* Channel Number Offset */
|
||||
|
||||
|
||||
/* Channel Address Register (R/W) */
|
||||
|
||||
#define CAR_CHAN 0x07 /* Channel Number Mask */
|
||||
|
||||
|
||||
/* Receive Character Status Register (R/O) */
|
||||
|
||||
#define RCSR_TOUT 0x80 /* Rx Timeout */
|
||||
#define RCSR_SCDET 0x70 /* Special Character Detected Mask */
|
||||
#define RCSR_NO_SC 0x00 /* No Special Characters Detected */
|
||||
#define RCSR_SC_1 0x10 /* Special Char 1 (or 1 & 3) Detected */
|
||||
#define RCSR_SC_2 0x20 /* Special Char 2 (or 2 & 4) Detected */
|
||||
#define RCSR_SC_3 0x30 /* Special Char 3 Detected */
|
||||
#define RCSR_SC_4 0x40 /* Special Char 4 Detected */
|
||||
#define RCSR_BREAK 0x08 /* Break has been detected */
|
||||
#define RCSR_PE 0x04 /* Parity Error */
|
||||
#define RCSR_FE 0x02 /* Frame Error */
|
||||
#define RCSR_OE 0x01 /* Overrun Error */
|
||||
|
||||
|
||||
/* Channel Command Register (R/W) (commands in groups can be OR-ed) */
|
||||
|
||||
#define CCR_HARDRESET 0x81 /* Reset the chip */
|
||||
|
||||
#define CCR_SOFTRESET 0x80 /* Soft Channel Reset */
|
||||
|
||||
#define CCR_CORCHG1 0x42 /* Channel Option Register 1 Changed */
|
||||
#define CCR_CORCHG2 0x44 /* Channel Option Register 2 Changed */
|
||||
#define CCR_CORCHG3 0x48 /* Channel Option Register 3 Changed */
|
||||
|
||||
#define CCR_SSCH1 0x21 /* Send Special Character 1 */
|
||||
|
||||
#define CCR_SSCH2 0x22 /* Send Special Character 2 */
|
||||
|
||||
#define CCR_SSCH3 0x23 /* Send Special Character 3 */
|
||||
|
||||
#define CCR_SSCH4 0x24 /* Send Special Character 4 */
|
||||
|
||||
#define CCR_TXEN 0x18 /* Enable Transmitter */
|
||||
#define CCR_RXEN 0x12 /* Enable Receiver */
|
||||
|
||||
#define CCR_TXDIS 0x14 /* Disable Transmitter */
|
||||
#define CCR_RXDIS 0x11 /* Disable Receiver */
|
||||
|
||||
|
||||
/* Service Request Enable Register (R/W) */
|
||||
|
||||
#define SRER_DSR 0x80 /* Enable interrupt on DSR change */
|
||||
#define SRER_CD 0x40 /* Enable interrupt on CD change */
|
||||
#define SRER_CTS 0x20 /* Enable interrupt on CTS change */
|
||||
#define SRER_RXD 0x10 /* Enable interrupt on Receive Data */
|
||||
#define SRER_RXSC 0x08 /* Enable interrupt on Receive Spec. Char */
|
||||
#define SRER_TXRDY 0x04 /* Enable interrupt on TX FIFO empty */
|
||||
#define SRER_TXEMPTY 0x02 /* Enable interrupt on TX completely empty */
|
||||
#define SRER_RET 0x01 /* Enable interrupt on RX Exc. Timeout */
|
||||
|
||||
|
||||
/* Channel Option Register 1 (R/W) */
|
||||
|
||||
#define COR1_ODDP 0x80 /* Odd Parity */
|
||||
#define COR1_PARMODE 0x60 /* Parity Mode mask */
|
||||
#define COR1_NOPAR 0x00 /* No Parity */
|
||||
#define COR1_FORCEPAR 0x20 /* Force Parity */
|
||||
#define COR1_NORMPAR 0x40 /* Normal Parity */
|
||||
#define COR1_IGNORE 0x10 /* Ignore Parity on RX */
|
||||
#define COR1_STOPBITS 0x0c /* Number of Stop Bits */
|
||||
#define COR1_1SB 0x00 /* 1 Stop Bit */
|
||||
#define COR1_15SB 0x04 /* 1.5 Stop Bits */
|
||||
#define COR1_2SB 0x08 /* 2 Stop Bits */
|
||||
#define COR1_CHARLEN 0x03 /* Character Length */
|
||||
#define COR1_5BITS 0x00 /* 5 bits */
|
||||
#define COR1_6BITS 0x01 /* 6 bits */
|
||||
#define COR1_7BITS 0x02 /* 7 bits */
|
||||
#define COR1_8BITS 0x03 /* 8 bits */
|
||||
|
||||
|
||||
/* Channel Option Register 2 (R/W) */
|
||||
|
||||
#define COR2_IXM 0x80 /* Implied XON mode */
|
||||
#define COR2_TXIBE 0x40 /* Enable In-Band (XON/XOFF) Flow Control */
|
||||
#define COR2_ETC 0x20 /* Embedded Tx Commands Enable */
|
||||
#define COR2_LLM 0x10 /* Local Loopback Mode */
|
||||
#define COR2_RLM 0x08 /* Remote Loopback Mode */
|
||||
#define COR2_RTSAO 0x04 /* RTS Automatic Output Enable */
|
||||
#define COR2_CTSAE 0x02 /* CTS Automatic Enable */
|
||||
#define COR2_DSRAE 0x01 /* DSR Automatic Enable */
|
||||
|
||||
|
||||
/* Channel Option Register 3 (R/W) */
|
||||
|
||||
#define COR3_XONCH 0x80 /* XON is a pair of characters (1 & 3) */
|
||||
#define COR3_XOFFCH 0x40 /* XOFF is a pair of characters (2 & 4) */
|
||||
#define COR3_FCT 0x20 /* Flow-Control Transparency Mode */
|
||||
#define COR3_SCDE 0x10 /* Special Character Detection Enable */
|
||||
#define COR3_RXTH 0x0f /* RX FIFO Threshold value (1-8) */
|
||||
|
||||
|
||||
/* Channel Control Status Register (R/O) */
|
||||
|
||||
#define CCSR_RXEN 0x80 /* Receiver Enabled */
|
||||
#define CCSR_RXFLOFF 0x40 /* Receive Flow Off (XOFF was sent) */
|
||||
#define CCSR_RXFLON 0x20 /* Receive Flow On (XON was sent) */
|
||||
#define CCSR_TXEN 0x08 /* Transmitter Enabled */
|
||||
#define CCSR_TXFLOFF 0x04 /* Transmit Flow Off (got XOFF) */
|
||||
#define CCSR_TXFLON 0x02 /* Transmit Flow On (got XON) */
|
||||
|
||||
|
||||
/* Modem Change Option Register 1 (R/W) */
|
||||
|
||||
#define MCOR1_DSRZD 0x80 /* Detect 0->1 transition of DSR */
|
||||
#define MCOR1_CDZD 0x40 /* Detect 0->1 transition of CD */
|
||||
#define MCOR1_CTSZD 0x20 /* Detect 0->1 transition of CTS */
|
||||
#define MCOR1_DTRTH 0x0f /* Auto DTR flow control Threshold (1-8) */
|
||||
#define MCOR1_NODTRFC 0x0 /* Automatic DTR flow control disabled */
|
||||
|
||||
|
||||
/* Modem Change Option Register 2 (R/W) */
|
||||
|
||||
#define MCOR2_DSROD 0x80 /* Detect 1->0 transition of DSR */
|
||||
#define MCOR2_CDOD 0x40 /* Detect 1->0 transition of CD */
|
||||
#define MCOR2_CTSOD 0x20 /* Detect 1->0 transition of CTS */
|
||||
|
||||
|
||||
/* Modem Change Register (R/W) */
|
||||
|
||||
#define MCR_DSRCHG 0x80 /* DSR Changed */
|
||||
#define MCR_CDCHG 0x40 /* CD Changed */
|
||||
#define MCR_CTSCHG 0x20 /* CTS Changed */
|
||||
|
||||
|
||||
/* Modem Signal Value Register (R/W) */
|
||||
|
||||
#define MSVR_DSR 0x80 /* Current state of DSR input */
|
||||
#define MSVR_CD 0x40 /* Current state of CD input */
|
||||
#define MSVR_CTS 0x20 /* Current state of CTS input */
|
||||
#define MSVR_DTR 0x02 /* Current state of DTR output */
|
||||
#define MSVR_RTS 0x01 /* Current state of RTS output */
|
||||
|
||||
|
||||
/* Service Request Status Register */
|
||||
|
||||
#define SRSR_CMASK 0xC0 /* Current Service Context Mask */
|
||||
#define SRSR_CNONE 0x00 /* Not in a service context */
|
||||
#define SRSR_CRX 0x40 /* Rx Context */
|
||||
#define SRSR_CTX 0x80 /* Tx Context */
|
||||
#define SRSR_CMDM 0xC0 /* Modem Context */
|
||||
#define SRSR_ANYINT 0x6F /* Any interrupt flag */
|
||||
#define SRSR_RINT 0x10 /* Receive Interrupt */
|
||||
#define SRSR_TINT 0x04 /* Transmit Interrupt */
|
||||
#define SRSR_MINT 0x01 /* Modem Interrupt */
|
||||
#define SRSR_REXT 0x20 /* Receive External Interrupt */
|
||||
#define SRSR_TEXT 0x08 /* Transmit External Interrupt */
|
||||
#define SRSR_MEXT 0x02 /* Modem External Interrupt */
|
||||
|
||||
|
||||
/* Service Request Configuration Register */
|
||||
|
||||
#define SRCR_PKGTYPE 0x80
|
||||
#define SRCR_REGACKEN 0x40
|
||||
#define SRCR_DAISYEN 0x20
|
||||
#define SRCR_GLOBPRI 0x10
|
||||
#define SRCR_UNFAIR 0x08
|
||||
#define SRCR_AUTOPRI 0x02
|
||||
#define SRCR_PRISEL 0x01
|
||||
|
||||
/* Values for register-based Interrupt ACKs */
|
||||
#define CD180_ACK_MINT 0x75 /* goes to MSMR */
|
||||
#define CD180_ACK_TINT 0x76 /* goes to TSMR */
|
||||
#define CD180_ACK_RINT 0x77 /* goes to RSMR */
|
||||
|
||||
/* Escape characters */
|
||||
|
||||
#define CD180_C_ESC 0x00 /* Escape character */
|
||||
#define CD180_C_SBRK 0x81 /* Start sending BREAK */
|
||||
#define CD180_C_DELAY 0x82 /* Delay output */
|
||||
#define CD180_C_EBRK 0x83 /* Stop sending BREAK */
|
||||
|
|
@ -364,6 +364,7 @@ static int __init ts102_uctrl_init(void)
|
|||
struct linux_prom_irqs tmp_irq[2];
|
||||
unsigned int vaddr[2] = { 0, 0 };
|
||||
int tmpnode, uctrlnode = prom_getchild(prom_root_node);
|
||||
int err;
|
||||
|
||||
tmpnode = prom_searchsiblings(uctrlnode, "obio");
|
||||
|
||||
|
|
@ -389,7 +390,12 @@ static int __init ts102_uctrl_init(void)
|
|||
if(!driver->irq)
|
||||
driver->irq = tmp_irq[0].pri;
|
||||
|
||||
request_irq(driver->irq, uctrl_interrupt, 0, "uctrl", driver);
|
||||
err = request_irq(driver->irq, uctrl_interrupt, 0, "uctrl", driver);
|
||||
if (err) {
|
||||
printk("%s: unable to register irq %d\n",
|
||||
__FUNCTION__, driver->irq);
|
||||
return err;
|
||||
}
|
||||
|
||||
if (misc_register(&uctrl_dev)) {
|
||||
printk("%s: unable to get misc minor %d\n",
|
||||
|
|
|
|||
Loading…
Reference in a new issue