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[PATCH] Improve data-dependency memory barrier example in documentation
In the memory barrier document, improve the example of the data dependency barrier situation by: (1) showing the initial values of the variables involved; and (2) repeating the instruction sequence description, this time with the data dependency barrier actually shown to make it clear what the revised sequence actually is. Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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@ -610,6 +610,7 @@ loads. Consider the following sequence of events:
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CPU 1 CPU 2
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======================= =======================
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{ B = 7; X = 9; Y = 8; C = &Y }
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STORE A = 1
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STORE B = 2
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<write barrier>
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@ -651,7 +652,20 @@ In the above example, CPU 2 perceives that B is 7, despite the load of *C
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(which would be B) coming after the the LOAD of C.
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If, however, a data dependency barrier were to be placed between the load of C
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and the load of *C (ie: B) on CPU 2, then the following will occur:
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and the load of *C (ie: B) on CPU 2:
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CPU 1 CPU 2
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======================= =======================
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{ B = 7; X = 9; Y = 8; C = &Y }
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STORE A = 1
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STORE B = 2
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<write barrier>
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STORE C = &B LOAD X
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STORE D = 4 LOAD C (gets &B)
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<data dependency barrier>
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LOAD *C (reads B)
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then the following will occur:
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+-------+ : : : :
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| | +------+ +-------+
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