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ALSA: ASoC: fix SNDCTL_DSP_SYNC support in Freescale 8610 sound drivers
If an OSS application calls SNDCTL_DSP_SYNC, then ALSA will call the driver's _hw_params and _prepare functions again. On the Freescale MPC8610 DMA ASoC driver, this caused the DMA controller to be unneccessarily re-programmed, and apparently it doesn't like that. The DMA will then not operate when instructed. This patch relocates much of the DMA programming to fsl_dma_open(), which is called only once. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
Timur Tabi
Takashi Iwai
parent
11589418a1
commit
bf9c8c9dde
1 changed files with 131 additions and 118 deletions
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@ -327,14 +327,75 @@ static int fsl_dma_new(struct snd_card *card, struct snd_soc_dai *dai,
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* fsl_dma_open: open a new substream.
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*
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* Each substream has its own DMA buffer.
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*
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* ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link
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* descriptors that ping-pong from one period to the next. For example, if
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* there are six periods and two link descriptors, this is how they look
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* before playback starts:
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*
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* The last link descriptor
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* ____________ points back to the first
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* | |
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* V |
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* ___ ___ |
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* | |->| |->|
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* |___| |___|
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* | |
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* | |
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* V V
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* _________________________________________
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* | | | | | | | The DMA buffer is
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* | | | | | | | divided into 6 parts
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* |______|______|______|______|______|______|
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*
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* and here's how they look after the first period is finished playing:
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*
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* ____________
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* | |
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* V |
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* ___ ___ |
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* | |->| |->|
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* |___| |___|
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* | |
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* |______________
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* | |
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* V V
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* _________________________________________
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* | | | | | | |
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* | | | | | | |
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* |______|______|______|______|______|______|
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*
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* The first link descriptor now points to the third period. The DMA
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* controller is currently playing the second period. When it finishes, it
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* will jump back to the first descriptor and play the third period.
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*
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* There are four reasons we do this:
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*
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* 1. The only way to get the DMA controller to automatically restart the
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* transfer when it gets to the end of the buffer is to use chaining
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* mode. Basic direct mode doesn't offer that feature.
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* 2. We need to receive an interrupt at the end of every period. The DMA
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* controller can generate an interrupt at the end of every link transfer
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* (aka segment). Making each period into a DMA segment will give us the
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* interrupts we need.
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* 3. By creating only two link descriptors, regardless of the number of
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* periods, we do not need to reallocate the link descriptors if the
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* number of periods changes.
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* 4. All of the audio data is still stored in a single, contiguous DMA
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* buffer, which is what ALSA expects. We're just dividing it into
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* contiguous parts, and creating a link descriptor for each one.
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*/
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static int fsl_dma_open(struct snd_pcm_substream *substream)
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{
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struct snd_pcm_runtime *runtime = substream->runtime;
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struct fsl_dma_private *dma_private;
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struct ccsr_dma_channel __iomem *dma_channel;
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dma_addr_t ld_buf_phys;
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u64 temp_link; /* Pointer to next link descriptor */
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u32 mr;
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unsigned int channel;
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int ret = 0;
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unsigned int i;
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/*
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* Reject any DMA buffer whose size is not a multiple of the period
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@ -395,135 +456,20 @@ static int fsl_dma_open(struct snd_pcm_substream *substream)
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snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware);
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runtime->private_data = dma_private;
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return 0;
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}
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/* Program the fixed DMA controller parameters */
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/**
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* fsl_dma_hw_params: allocate the DMA buffer and the DMA link descriptors.
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*
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* ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link
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* descriptors that ping-pong from one period to the next. For example, if
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* there are six periods and two link descriptors, this is how they look
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* before playback starts:
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*
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* The last link descriptor
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* ____________ points back to the first
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* | |
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* V |
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* ___ ___ |
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* | |->| |->|
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* |___| |___|
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* | |
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* | |
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* V V
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* _________________________________________
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* | | | | | | | The DMA buffer is
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* | | | | | | | divided into 6 parts
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* |______|______|______|______|______|______|
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*
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* and here's how they look after the first period is finished playing:
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*
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* ____________
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* | |
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* V |
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* ___ ___ |
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* | |->| |->|
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* |___| |___|
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* | |
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* |______________
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* | |
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* V V
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* _________________________________________
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* | | | | | | |
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* | | | | | | |
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* |______|______|______|______|______|______|
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*
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* The first link descriptor now points to the third period. The DMA
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* controller is currently playing the second period. When it finishes, it
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* will jump back to the first descriptor and play the third period.
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*
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* There are four reasons we do this:
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*
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* 1. The only way to get the DMA controller to automatically restart the
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* transfer when it gets to the end of the buffer is to use chaining
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* mode. Basic direct mode doesn't offer that feature.
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* 2. We need to receive an interrupt at the end of every period. The DMA
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* controller can generate an interrupt at the end of every link transfer
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* (aka segment). Making each period into a DMA segment will give us the
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* interrupts we need.
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* 3. By creating only two link descriptors, regardless of the number of
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* periods, we do not need to reallocate the link descriptors if the
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* number of periods changes.
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* 4. All of the audio data is still stored in a single, contiguous DMA
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* buffer, which is what ALSA expects. We're just dividing it into
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* contiguous parts, and creating a link descriptor for each one.
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*
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* Note that due to a quirk of the SSI's STX register, the target address
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* for the DMA operations depends on the sample size. So we don't program
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* the dest_addr (for playback -- source_addr for capture) fields in the
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* link descriptors here. We do that in fsl_dma_prepare()
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*/
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static int fsl_dma_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *hw_params)
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{
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struct snd_pcm_runtime *runtime = substream->runtime;
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struct fsl_dma_private *dma_private = runtime->private_data;
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struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
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dma_channel = dma_private->dma_channel;
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dma_addr_t temp_addr; /* Pointer to next period */
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u64 temp_link; /* Pointer to next link descriptor */
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u32 mr; /* Temporary variable for MR register */
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unsigned int i;
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/* Get all the parameters we need */
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size_t buffer_size = params_buffer_bytes(hw_params);
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size_t period_size = params_period_bytes(hw_params);
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/* Initialize our DMA tracking variables */
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dma_private->period_size = period_size;
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dma_private->num_periods = params_periods(hw_params);
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dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size;
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dma_private->dma_buf_next = dma_private->dma_buf_phys +
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(NUM_DMA_LINKS * period_size);
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if (dma_private->dma_buf_next >= dma_private->dma_buf_end)
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dma_private->dma_buf_next = dma_private->dma_buf_phys;
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/*
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* Initialize each link descriptor.
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*
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* The actual address in STX0 (destination for playback, source for
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* capture) is based on the sample size, but we don't know the sample
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* size in this function, so we'll have to adjust that later. See
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* comments in fsl_dma_prepare().
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*
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* The DMA controller does not have a cache, so the CPU does not
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* need to tell it to flush its cache. However, the DMA
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* controller does need to tell the CPU to flush its cache.
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* That's what the SNOOP bit does.
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*
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* Also, even though the DMA controller supports 36-bit addressing, for
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* simplicity we currently support only 32-bit addresses for the audio
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* buffer itself.
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*/
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temp_addr = substream->dma_buffer.addr;
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temp_link = dma_private->ld_buf_phys +
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sizeof(struct fsl_dma_link_descriptor);
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for (i = 0; i < NUM_DMA_LINKS; i++) {
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struct fsl_dma_link_descriptor *link = &dma_private->link[i];
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link->count = cpu_to_be32(period_size);
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link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP);
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link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP);
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link->next = cpu_to_be64(temp_link);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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link->source_addr = cpu_to_be32(temp_addr);
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else
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link->dest_addr = cpu_to_be32(temp_addr);
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temp_addr += period_size;
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temp_link += sizeof(struct fsl_dma_link_descriptor);
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}
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/* The last link descriptor points to the first */
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@ -549,7 +495,7 @@ static int fsl_dma_hw_params(struct snd_pcm_substream *substream,
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* We want External Master Start and External Master Pause enabled,
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* because the SSI is controlling the DMA controller. We want the DMA
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* controller to be set up in advance, and then we signal only the SSI
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* to start transfering.
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* to start transferring.
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*
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* We want End-Of-Segment Interrupts enabled, because this will generate
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* an interrupt at the end of each segment (each link descriptor
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@ -573,6 +519,73 @@ static int fsl_dma_hw_params(struct snd_pcm_substream *substream,
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return 0;
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}
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/**
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* fsl_dma_hw_params: continue initializing the DMA links
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*
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* This function obtains hardware parameters about the opened stream and
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* programs the DMA controller accordingly.
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*
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* Note that due to a quirk of the SSI's STX register, the target address
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* for the DMA operations depends on the sample size. So we don't program
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* the dest_addr (for playback -- source_addr for capture) fields in the
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* link descriptors here. We do that in fsl_dma_prepare()
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*/
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static int fsl_dma_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *hw_params)
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{
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struct snd_pcm_runtime *runtime = substream->runtime;
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struct fsl_dma_private *dma_private = runtime->private_data;
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dma_addr_t temp_addr; /* Pointer to next period */
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unsigned int i;
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/* Get all the parameters we need */
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size_t buffer_size = params_buffer_bytes(hw_params);
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size_t period_size = params_period_bytes(hw_params);
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/* Initialize our DMA tracking variables */
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dma_private->period_size = period_size;
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dma_private->num_periods = params_periods(hw_params);
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dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size;
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dma_private->dma_buf_next = dma_private->dma_buf_phys +
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(NUM_DMA_LINKS * period_size);
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if (dma_private->dma_buf_next >= dma_private->dma_buf_end)
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dma_private->dma_buf_next = dma_private->dma_buf_phys;
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/*
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* The actual address in STX0 (destination for playback, source for
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* capture) is based on the sample size, but we don't know the sample
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* size in this function, so we'll have to adjust that later. See
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* comments in fsl_dma_prepare().
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*
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* The DMA controller does not have a cache, so the CPU does not
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* need to tell it to flush its cache. However, the DMA
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* controller does need to tell the CPU to flush its cache.
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* That's what the SNOOP bit does.
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*
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* Also, even though the DMA controller supports 36-bit addressing, for
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* simplicity we currently support only 32-bit addresses for the audio
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* buffer itself.
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*/
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temp_addr = substream->dma_buffer.addr;
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for (i = 0; i < NUM_DMA_LINKS; i++) {
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struct fsl_dma_link_descriptor *link = &dma_private->link[i];
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link->count = cpu_to_be32(period_size);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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link->source_addr = cpu_to_be32(temp_addr);
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else
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link->dest_addr = cpu_to_be32(temp_addr);
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temp_addr += period_size;
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}
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return 0;
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}
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/**
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* fsl_dma_prepare - prepare the DMA registers for playback.
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*
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