mirror of
https://github.com/adulau/aha.git
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Merge branch 'next-spi' of git://git.secretlab.ca/git/linux-2.6
* 'next-spi' of git://git.secretlab.ca/git/linux-2.6: spi: spi_txx9.c: use resource_size() spi: spi_sh_sci.c: use resource_size() spi: spi_mpc8xxx.c: use resource_size() spi: spi_bfin5xx.c: use resource_size() spi: atmel_spi.c: use resource_size() spi: Add s3c64xx SPI Controller driver atmel_spi: fix dma addr calculation for len > BUFFER_SIZE spi_s3c24xx: add FIQ pseudo-DMA support spi: controller driver for Designware SPI core spidev: add proper section markers spidev: use DECLARE_BITMAP instead of declaring the array
This commit is contained in:
Linus Torvalds
commit
bf931a01a2
16 changed files with 2950 additions and 33 deletions
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@ -18,6 +18,8 @@ struct s3c2410_spi_info {
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unsigned int num_cs; /* total chipselects */
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unsigned int num_cs; /* total chipselects */
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int bus_num; /* bus number to use. */
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int bus_num; /* bus number to use. */
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unsigned int use_fiq:1; /* use fiq */
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void (*gpio_setup)(struct s3c2410_spi_info *spi, int enable);
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void (*gpio_setup)(struct s3c2410_spi_info *spi, int enable);
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void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol);
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void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol);
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};
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};
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@ -216,6 +216,17 @@ config SPI_S3C24XX
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help
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help
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SPI driver for Samsung S3C24XX series ARM SoCs
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SPI driver for Samsung S3C24XX series ARM SoCs
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config SPI_S3C24XX_FIQ
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bool "S3C24XX driver with FIQ pseudo-DMA"
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depends on SPI_S3C24XX
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select FIQ
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help
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Enable FIQ support for the S3C24XX SPI driver to provide pseudo
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DMA by using the fast-interrupt request framework, This allows
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the driver to get DMA-like performance when there are either
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no free DMA channels, or when doing transfers that required both
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TX and RX data paths.
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config SPI_S3C24XX_GPIO
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config SPI_S3C24XX_GPIO
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tristate "Samsung S3C24XX series SPI by GPIO"
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tristate "Samsung S3C24XX series SPI by GPIO"
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depends on ARCH_S3C2410 && EXPERIMENTAL
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depends on ARCH_S3C2410 && EXPERIMENTAL
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@ -226,6 +237,13 @@ config SPI_S3C24XX_GPIO
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the inbuilt hardware cannot provide the transfer mode, or
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the inbuilt hardware cannot provide the transfer mode, or
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where the board is using non hardware connected pins.
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where the board is using non hardware connected pins.
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config SPI_S3C64XX
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tristate "Samsung S3C64XX series type SPI"
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depends on ARCH_S3C64XX && EXPERIMENTAL
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select S3C64XX_DMA
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help
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SPI driver for Samsung S3C64XX and newer SoCs.
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config SPI_SH_MSIOF
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config SPI_SH_MSIOF
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tristate "SuperH MSIOF SPI controller"
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tristate "SuperH MSIOF SPI controller"
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depends on SUPERH && HAVE_CLK
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depends on SUPERH && HAVE_CLK
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@ -289,6 +307,16 @@ config SPI_NUC900
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# Add new SPI master controllers in alphabetical order above this line
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# Add new SPI master controllers in alphabetical order above this line
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#
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#
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config SPI_DESIGNWARE
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bool "DesignWare SPI controller core support"
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depends on SPI_MASTER
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help
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general driver for SPI controller core from DesignWare
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config SPI_DW_PCI
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tristate "PCI interface driver for DW SPI core"
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depends on SPI_DESIGNWARE && PCI
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#
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#
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# There are lots of SPI device types, with sensors and memory
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# There are lots of SPI device types, with sensors and memory
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# being probably the most widely used ones.
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# being probably the most widely used ones.
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@ -16,6 +16,8 @@ obj-$(CONFIG_SPI_BFIN) += spi_bfin5xx.o
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obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o
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obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o
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obj-$(CONFIG_SPI_AU1550) += au1550_spi.o
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obj-$(CONFIG_SPI_AU1550) += au1550_spi.o
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obj-$(CONFIG_SPI_BUTTERFLY) += spi_butterfly.o
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obj-$(CONFIG_SPI_BUTTERFLY) += spi_butterfly.o
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obj-$(CONFIG_SPI_DESIGNWARE) += dw_spi.o
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obj-$(CONFIG_SPI_DW_PCI) += dw_spi_pci.o
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obj-$(CONFIG_SPI_GPIO) += spi_gpio.o
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obj-$(CONFIG_SPI_GPIO) += spi_gpio.o
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obj-$(CONFIG_SPI_IMX) += spi_imx.o
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obj-$(CONFIG_SPI_IMX) += spi_imx.o
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obj-$(CONFIG_SPI_LM70_LLP) += spi_lm70llp.o
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obj-$(CONFIG_SPI_LM70_LLP) += spi_lm70llp.o
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@ -30,7 +32,8 @@ obj-$(CONFIG_SPI_MPC52xx) += mpc52xx_spi.o
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obj-$(CONFIG_SPI_MPC8xxx) += spi_mpc8xxx.o
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obj-$(CONFIG_SPI_MPC8xxx) += spi_mpc8xxx.o
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obj-$(CONFIG_SPI_PPC4xx) += spi_ppc4xx.o
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obj-$(CONFIG_SPI_PPC4xx) += spi_ppc4xx.o
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obj-$(CONFIG_SPI_S3C24XX_GPIO) += spi_s3c24xx_gpio.o
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obj-$(CONFIG_SPI_S3C24XX_GPIO) += spi_s3c24xx_gpio.o
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obj-$(CONFIG_SPI_S3C24XX) += spi_s3c24xx.o
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obj-$(CONFIG_SPI_S3C24XX) += spi_s3c24xx_hw.o
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obj-$(CONFIG_SPI_S3C64XX) += spi_s3c64xx.o
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obj-$(CONFIG_SPI_TXX9) += spi_txx9.o
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obj-$(CONFIG_SPI_TXX9) += spi_txx9.o
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obj-$(CONFIG_SPI_XILINX) += xilinx_spi.o
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obj-$(CONFIG_SPI_XILINX) += xilinx_spi.o
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obj-$(CONFIG_SPI_XILINX_OF) += xilinx_spi_of.o
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obj-$(CONFIG_SPI_XILINX_OF) += xilinx_spi_of.o
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@ -39,6 +42,11 @@ obj-$(CONFIG_SPI_SH_SCI) += spi_sh_sci.o
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obj-$(CONFIG_SPI_SH_MSIOF) += spi_sh_msiof.o
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obj-$(CONFIG_SPI_SH_MSIOF) += spi_sh_msiof.o
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obj-$(CONFIG_SPI_STMP3XXX) += spi_stmp.o
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obj-$(CONFIG_SPI_STMP3XXX) += spi_stmp.o
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obj-$(CONFIG_SPI_NUC900) += spi_nuc900.o
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obj-$(CONFIG_SPI_NUC900) += spi_nuc900.o
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# special build for s3c24xx spi driver with fiq support
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spi_s3c24xx_hw-y := spi_s3c24xx.o
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spi_s3c24xx_hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi_s3c24xx_fiq.o
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# ... add above this line ...
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# ... add above this line ...
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# SPI protocol drivers (device/link on bus)
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# SPI protocol drivers (device/link on bus)
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@ -189,14 +189,14 @@ static void atmel_spi_next_xfer_data(struct spi_master *master,
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/* use scratch buffer only when rx or tx data is unspecified */
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/* use scratch buffer only when rx or tx data is unspecified */
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if (xfer->rx_buf)
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if (xfer->rx_buf)
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*rx_dma = xfer->rx_dma + xfer->len - len;
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*rx_dma = xfer->rx_dma + xfer->len - *plen;
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else {
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else {
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*rx_dma = as->buffer_dma;
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*rx_dma = as->buffer_dma;
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if (len > BUFFER_SIZE)
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if (len > BUFFER_SIZE)
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len = BUFFER_SIZE;
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len = BUFFER_SIZE;
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}
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}
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if (xfer->tx_buf)
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if (xfer->tx_buf)
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*tx_dma = xfer->tx_dma + xfer->len - len;
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*tx_dma = xfer->tx_dma + xfer->len - *plen;
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else {
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else {
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*tx_dma = as->buffer_dma;
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*tx_dma = as->buffer_dma;
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if (len > BUFFER_SIZE)
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if (len > BUFFER_SIZE)
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@ -788,7 +788,7 @@ static int __init atmel_spi_probe(struct platform_device *pdev)
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spin_lock_init(&as->lock);
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spin_lock_init(&as->lock);
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INIT_LIST_HEAD(&as->queue);
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INIT_LIST_HEAD(&as->queue);
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as->pdev = pdev;
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as->pdev = pdev;
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as->regs = ioremap(regs->start, (regs->end - regs->start) + 1);
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as->regs = ioremap(regs->start, resource_size(regs));
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if (!as->regs)
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if (!as->regs)
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goto out_free_buffer;
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goto out_free_buffer;
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as->irq = irq;
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as->irq = irq;
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944
drivers/spi/dw_spi.c
Normal file
944
drivers/spi/dw_spi.c
Normal file
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@ -0,0 +1,944 @@
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/*
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* dw_spi.c - Designware SPI core controller driver (refer pxa2xx_spi.c)
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*
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* Copyright (c) 2009, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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||||||
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*
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||||||
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* You should have received a copy of the GNU General Public License along with
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||||||
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include <linux/dma-mapping.h>
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#include <linux/interrupt.h>
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#include <linux/highmem.h>
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#include <linux/delay.h>
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#include <linux/spi/dw_spi.h>
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#include <linux/spi/spi.h>
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#ifdef CONFIG_DEBUG_FS
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#include <linux/debugfs.h>
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#endif
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#define START_STATE ((void *)0)
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#define RUNNING_STATE ((void *)1)
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#define DONE_STATE ((void *)2)
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#define ERROR_STATE ((void *)-1)
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#define QUEUE_RUNNING 0
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#define QUEUE_STOPPED 1
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#define MRST_SPI_DEASSERT 0
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#define MRST_SPI_ASSERT 1
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/* Slave spi_dev related */
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struct chip_data {
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u16 cr0;
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u8 cs; /* chip select pin */
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u8 n_bytes; /* current is a 1/2/4 byte op */
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u8 tmode; /* TR/TO/RO/EEPROM */
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u8 type; /* SPI/SSP/MicroWire */
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u8 poll_mode; /* 1 means use poll mode */
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u32 dma_width;
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u32 rx_threshold;
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u32 tx_threshold;
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u8 enable_dma;
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u8 bits_per_word;
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u16 clk_div; /* baud rate divider */
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u32 speed_hz; /* baud rate */
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int (*write)(struct dw_spi *dws);
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int (*read)(struct dw_spi *dws);
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||||||
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void (*cs_control)(u32 command);
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};
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#ifdef CONFIG_DEBUG_FS
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static int spi_show_regs_open(struct inode *inode, struct file *file)
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|
{
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||||||
|
file->private_data = inode->i_private;
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return 0;
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||||||
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}
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||||||
|
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||||||
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#define SPI_REGS_BUFSIZE 1024
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static ssize_t spi_show_regs(struct file *file, char __user *user_buf,
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size_t count, loff_t *ppos)
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||||||
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{
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||||||
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struct dw_spi *dws;
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||||||
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char *buf;
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||||||
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u32 len = 0;
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||||||
|
ssize_t ret;
|
||||||
|
|
||||||
|
dws = file->private_data;
|
||||||
|
|
||||||
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buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
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||||||
|
if (!buf)
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||||||
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return 0;
|
||||||
|
|
||||||
|
len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
|
||||||
|
"MRST SPI0 registers:\n");
|
||||||
|
len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
|
||||||
|
"=================================\n");
|
||||||
|
len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
|
||||||
|
"CTRL0: \t\t0x%08x\n", dw_readl(dws, ctrl0));
|
||||||
|
len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
|
||||||
|
"CTRL1: \t\t0x%08x\n", dw_readl(dws, ctrl1));
|
||||||
|
len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
|
||||||
|
"SSIENR: \t0x%08x\n", dw_readl(dws, ssienr));
|
||||||
|
len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
|
||||||
|
"SER: \t\t0x%08x\n", dw_readl(dws, ser));
|
||||||
|
len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
|
||||||
|
"BAUDR: \t\t0x%08x\n", dw_readl(dws, baudr));
|
||||||
|
len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
|
||||||
|
"TXFTLR: \t0x%08x\n", dw_readl(dws, txfltr));
|
||||||
|
len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
|
||||||
|
"RXFTLR: \t0x%08x\n", dw_readl(dws, rxfltr));
|
||||||
|
len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
|
||||||
|
"TXFLR: \t\t0x%08x\n", dw_readl(dws, txflr));
|
||||||
|
len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
|
||||||
|
"RXFLR: \t\t0x%08x\n", dw_readl(dws, rxflr));
|
||||||
|
len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
|
||||||
|
"SR: \t\t0x%08x\n", dw_readl(dws, sr));
|
||||||
|
len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
|
||||||
|
"IMR: \t\t0x%08x\n", dw_readl(dws, imr));
|
||||||
|
len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
|
||||||
|
"ISR: \t\t0x%08x\n", dw_readl(dws, isr));
|
||||||
|
len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
|
||||||
|
"DMACR: \t\t0x%08x\n", dw_readl(dws, dmacr));
|
||||||
|
len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
|
||||||
|
"DMATDLR: \t0x%08x\n", dw_readl(dws, dmatdlr));
|
||||||
|
len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
|
||||||
|
"DMARDLR: \t0x%08x\n", dw_readl(dws, dmardlr));
|
||||||
|
len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
|
||||||
|
"=================================\n");
|
||||||
|
|
||||||
|
ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
|
||||||
|
kfree(buf);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct file_operations mrst_spi_regs_ops = {
|
||||||
|
.owner = THIS_MODULE,
|
||||||
|
.open = spi_show_regs_open,
|
||||||
|
.read = spi_show_regs,
|
||||||
|
};
|
||||||
|
|
||||||
|
static int mrst_spi_debugfs_init(struct dw_spi *dws)
|
||||||
|
{
|
||||||
|
dws->debugfs = debugfs_create_dir("mrst_spi", NULL);
|
||||||
|
if (!dws->debugfs)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
debugfs_create_file("registers", S_IFREG | S_IRUGO,
|
||||||
|
dws->debugfs, (void *)dws, &mrst_spi_regs_ops);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void mrst_spi_debugfs_remove(struct dw_spi *dws)
|
||||||
|
{
|
||||||
|
if (dws->debugfs)
|
||||||
|
debugfs_remove_recursive(dws->debugfs);
|
||||||
|
}
|
||||||
|
|
||||||
|
#else
|
||||||
|
static inline int mrst_spi_debugfs_init(struct dw_spi *dws)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void mrst_spi_debugfs_remove(struct dw_spi *dws)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
#endif /* CONFIG_DEBUG_FS */
|
||||||
|
|
||||||
|
static void wait_till_not_busy(struct dw_spi *dws)
|
||||||
|
{
|
||||||
|
unsigned long end = jiffies + usecs_to_jiffies(1000);
|
||||||
|
|
||||||
|
while (time_before(jiffies, end)) {
|
||||||
|
if (!(dw_readw(dws, sr) & SR_BUSY))
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
dev_err(&dws->master->dev,
|
||||||
|
"DW SPI: Stutus keeps busy for 1000us after a read/write!\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
static void flush(struct dw_spi *dws)
|
||||||
|
{
|
||||||
|
while (dw_readw(dws, sr) & SR_RF_NOT_EMPT)
|
||||||
|
dw_readw(dws, dr);
|
||||||
|
|
||||||
|
wait_till_not_busy(dws);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void null_cs_control(u32 command)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
static int null_writer(struct dw_spi *dws)
|
||||||
|
{
|
||||||
|
u8 n_bytes = dws->n_bytes;
|
||||||
|
|
||||||
|
if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
|
||||||
|
|| (dws->tx == dws->tx_end))
|
||||||
|
return 0;
|
||||||
|
dw_writew(dws, dr, 0);
|
||||||
|
dws->tx += n_bytes;
|
||||||
|
|
||||||
|
wait_till_not_busy(dws);
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int null_reader(struct dw_spi *dws)
|
||||||
|
{
|
||||||
|
u8 n_bytes = dws->n_bytes;
|
||||||
|
|
||||||
|
while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
|
||||||
|
&& (dws->rx < dws->rx_end)) {
|
||||||
|
dw_readw(dws, dr);
|
||||||
|
dws->rx += n_bytes;
|
||||||
|
}
|
||||||
|
wait_till_not_busy(dws);
|
||||||
|
return dws->rx == dws->rx_end;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int u8_writer(struct dw_spi *dws)
|
||||||
|
{
|
||||||
|
if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
|
||||||
|
|| (dws->tx == dws->tx_end))
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
dw_writew(dws, dr, *(u8 *)(dws->tx));
|
||||||
|
++dws->tx;
|
||||||
|
|
||||||
|
wait_till_not_busy(dws);
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int u8_reader(struct dw_spi *dws)
|
||||||
|
{
|
||||||
|
while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
|
||||||
|
&& (dws->rx < dws->rx_end)) {
|
||||||
|
*(u8 *)(dws->rx) = dw_readw(dws, dr);
|
||||||
|
++dws->rx;
|
||||||
|
}
|
||||||
|
|
||||||
|
wait_till_not_busy(dws);
|
||||||
|
return dws->rx == dws->rx_end;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int u16_writer(struct dw_spi *dws)
|
||||||
|
{
|
||||||
|
if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
|
||||||
|
|| (dws->tx == dws->tx_end))
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
dw_writew(dws, dr, *(u16 *)(dws->tx));
|
||||||
|
dws->tx += 2;
|
||||||
|
|
||||||
|
wait_till_not_busy(dws);
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int u16_reader(struct dw_spi *dws)
|
||||||
|
{
|
||||||
|
u16 temp;
|
||||||
|
|
||||||
|
while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
|
||||||
|
&& (dws->rx < dws->rx_end)) {
|
||||||
|
temp = dw_readw(dws, dr);
|
||||||
|
*(u16 *)(dws->rx) = temp;
|
||||||
|
dws->rx += 2;
|
||||||
|
}
|
||||||
|
|
||||||
|
wait_till_not_busy(dws);
|
||||||
|
return dws->rx == dws->rx_end;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void *next_transfer(struct dw_spi *dws)
|
||||||
|
{
|
||||||
|
struct spi_message *msg = dws->cur_msg;
|
||||||
|
struct spi_transfer *trans = dws->cur_transfer;
|
||||||
|
|
||||||
|
/* Move to next transfer */
|
||||||
|
if (trans->transfer_list.next != &msg->transfers) {
|
||||||
|
dws->cur_transfer =
|
||||||
|
list_entry(trans->transfer_list.next,
|
||||||
|
struct spi_transfer,
|
||||||
|
transfer_list);
|
||||||
|
return RUNNING_STATE;
|
||||||
|
} else
|
||||||
|
return DONE_STATE;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Note: first step is the protocol driver prepares
|
||||||
|
* a dma-capable memory, and this func just need translate
|
||||||
|
* the virt addr to physical
|
||||||
|
*/
|
||||||
|
static int map_dma_buffers(struct dw_spi *dws)
|
||||||
|
{
|
||||||
|
if (!dws->cur_msg->is_dma_mapped || !dws->dma_inited
|
||||||
|
|| !dws->cur_chip->enable_dma)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
if (dws->cur_transfer->tx_dma)
|
||||||
|
dws->tx_dma = dws->cur_transfer->tx_dma;
|
||||||
|
|
||||||
|
if (dws->cur_transfer->rx_dma)
|
||||||
|
dws->rx_dma = dws->cur_transfer->rx_dma;
|
||||||
|
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Caller already set message->status; dma and pio irqs are blocked */
|
||||||
|
static void giveback(struct dw_spi *dws)
|
||||||
|
{
|
||||||
|
struct spi_transfer *last_transfer;
|
||||||
|
unsigned long flags;
|
||||||
|
struct spi_message *msg;
|
||||||
|
|
||||||
|
spin_lock_irqsave(&dws->lock, flags);
|
||||||
|
msg = dws->cur_msg;
|
||||||
|
dws->cur_msg = NULL;
|
||||||
|
dws->cur_transfer = NULL;
|
||||||
|
dws->prev_chip = dws->cur_chip;
|
||||||
|
dws->cur_chip = NULL;
|
||||||
|
dws->dma_mapped = 0;
|
||||||
|
queue_work(dws->workqueue, &dws->pump_messages);
|
||||||
|
spin_unlock_irqrestore(&dws->lock, flags);
|
||||||
|
|
||||||
|
last_transfer = list_entry(msg->transfers.prev,
|
||||||
|
struct spi_transfer,
|
||||||
|
transfer_list);
|
||||||
|
|
||||||
|
if (!last_transfer->cs_change)
|
||||||
|
dws->cs_control(MRST_SPI_DEASSERT);
|
||||||
|
|
||||||
|
msg->state = NULL;
|
||||||
|
if (msg->complete)
|
||||||
|
msg->complete(msg->context);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void int_error_stop(struct dw_spi *dws, const char *msg)
|
||||||
|
{
|
||||||
|
/* Stop and reset hw */
|
||||||
|
flush(dws);
|
||||||
|
spi_enable_chip(dws, 0);
|
||||||
|
|
||||||
|
dev_err(&dws->master->dev, "%s\n", msg);
|
||||||
|
dws->cur_msg->state = ERROR_STATE;
|
||||||
|
tasklet_schedule(&dws->pump_transfers);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void transfer_complete(struct dw_spi *dws)
|
||||||
|
{
|
||||||
|
/* Update total byte transfered return count actual bytes read */
|
||||||
|
dws->cur_msg->actual_length += dws->len;
|
||||||
|
|
||||||
|
/* Move to next transfer */
|
||||||
|
dws->cur_msg->state = next_transfer(dws);
|
||||||
|
|
||||||
|
/* Handle end of message */
|
||||||
|
if (dws->cur_msg->state == DONE_STATE) {
|
||||||
|
dws->cur_msg->status = 0;
|
||||||
|
giveback(dws);
|
||||||
|
} else
|
||||||
|
tasklet_schedule(&dws->pump_transfers);
|
||||||
|
}
|
||||||
|
|
||||||
|
static irqreturn_t interrupt_transfer(struct dw_spi *dws)
|
||||||
|
{
|
||||||
|
u16 irq_status, irq_mask = 0x3f;
|
||||||
|
|
||||||
|
irq_status = dw_readw(dws, isr) & irq_mask;
|
||||||
|
/* Error handling */
|
||||||
|
if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
|
||||||
|
dw_readw(dws, txoicr);
|
||||||
|
dw_readw(dws, rxoicr);
|
||||||
|
dw_readw(dws, rxuicr);
|
||||||
|
int_error_stop(dws, "interrupt_transfer: fifo overrun");
|
||||||
|
return IRQ_HANDLED;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* INT comes from tx */
|
||||||
|
if (dws->tx && (irq_status & SPI_INT_TXEI)) {
|
||||||
|
while (dws->tx < dws->tx_end)
|
||||||
|
dws->write(dws);
|
||||||
|
|
||||||
|
if (dws->tx == dws->tx_end) {
|
||||||
|
spi_mask_intr(dws, SPI_INT_TXEI);
|
||||||
|
transfer_complete(dws);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* INT comes from rx */
|
||||||
|
if (dws->rx && (irq_status & SPI_INT_RXFI)) {
|
||||||
|
if (dws->read(dws))
|
||||||
|
transfer_complete(dws);
|
||||||
|
}
|
||||||
|
return IRQ_HANDLED;
|
||||||
|
}
|
||||||
|
|
||||||
|
static irqreturn_t dw_spi_irq(int irq, void *dev_id)
|
||||||
|
{
|
||||||
|
struct dw_spi *dws = dev_id;
|
||||||
|
|
||||||
|
if (!dws->cur_msg) {
|
||||||
|
spi_mask_intr(dws, SPI_INT_TXEI);
|
||||||
|
/* Never fail */
|
||||||
|
return IRQ_HANDLED;
|
||||||
|
}
|
||||||
|
|
||||||
|
return dws->transfer_handler(dws);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Must be called inside pump_transfers() */
|
||||||
|
static void poll_transfer(struct dw_spi *dws)
|
||||||
|
{
|
||||||
|
if (dws->tx) {
|
||||||
|
while (dws->write(dws))
|
||||||
|
dws->read(dws);
|
||||||
|
}
|
||||||
|
|
||||||
|
dws->read(dws);
|
||||||
|
transfer_complete(dws);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void dma_transfer(struct dw_spi *dws, int cs_change)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
static void pump_transfers(unsigned long data)
|
||||||
|
{
|
||||||
|
struct dw_spi *dws = (struct dw_spi *)data;
|
||||||
|
struct spi_message *message = NULL;
|
||||||
|
struct spi_transfer *transfer = NULL;
|
||||||
|
struct spi_transfer *previous = NULL;
|
||||||
|
struct spi_device *spi = NULL;
|
||||||
|
struct chip_data *chip = NULL;
|
||||||
|
u8 bits = 0;
|
||||||
|
u8 imask = 0;
|
||||||
|
u8 cs_change = 0;
|
||||||
|
u16 clk_div = 0;
|
||||||
|
u32 speed = 0;
|
||||||
|
u32 cr0 = 0;
|
||||||
|
|
||||||
|
/* Get current state information */
|
||||||
|
message = dws->cur_msg;
|
||||||
|
transfer = dws->cur_transfer;
|
||||||
|
chip = dws->cur_chip;
|
||||||
|
spi = message->spi;
|
||||||
|
|
||||||
|
if (message->state == ERROR_STATE) {
|
||||||
|
message->status = -EIO;
|
||||||
|
goto early_exit;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Handle end of message */
|
||||||
|
if (message->state == DONE_STATE) {
|
||||||
|
message->status = 0;
|
||||||
|
goto early_exit;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Delay if requested at end of transfer*/
|
||||||
|
if (message->state == RUNNING_STATE) {
|
||||||
|
previous = list_entry(transfer->transfer_list.prev,
|
||||||
|
struct spi_transfer,
|
||||||
|
transfer_list);
|
||||||
|
if (previous->delay_usecs)
|
||||||
|
udelay(previous->delay_usecs);
|
||||||
|
}
|
||||||
|
|
||||||
|
dws->n_bytes = chip->n_bytes;
|
||||||
|
dws->dma_width = chip->dma_width;
|
||||||
|
dws->cs_control = chip->cs_control;
|
||||||
|
|
||||||
|
dws->rx_dma = transfer->rx_dma;
|
||||||
|
dws->tx_dma = transfer->tx_dma;
|
||||||
|
dws->tx = (void *)transfer->tx_buf;
|
||||||
|
dws->tx_end = dws->tx + transfer->len;
|
||||||
|
dws->rx = transfer->rx_buf;
|
||||||
|
dws->rx_end = dws->rx + transfer->len;
|
||||||
|
dws->write = dws->tx ? chip->write : null_writer;
|
||||||
|
dws->read = dws->rx ? chip->read : null_reader;
|
||||||
|
dws->cs_change = transfer->cs_change;
|
||||||
|
dws->len = dws->cur_transfer->len;
|
||||||
|
if (chip != dws->prev_chip)
|
||||||
|
cs_change = 1;
|
||||||
|
|
||||||
|
cr0 = chip->cr0;
|
||||||
|
|
||||||
|
/* Handle per transfer options for bpw and speed */
|
||||||
|
if (transfer->speed_hz) {
|
||||||
|
speed = chip->speed_hz;
|
||||||
|
|
||||||
|
if (transfer->speed_hz != speed) {
|
||||||
|
speed = transfer->speed_hz;
|
||||||
|
if (speed > dws->max_freq) {
|
||||||
|
printk(KERN_ERR "MRST SPI0: unsupported"
|
||||||
|
"freq: %dHz\n", speed);
|
||||||
|
message->status = -EIO;
|
||||||
|
goto early_exit;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* clk_div doesn't support odd number */
|
||||||
|
clk_div = dws->max_freq / speed;
|
||||||
|
clk_div = (clk_div >> 1) << 1;
|
||||||
|
|
||||||
|
chip->speed_hz = speed;
|
||||||
|
chip->clk_div = clk_div;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
if (transfer->bits_per_word) {
|
||||||
|
bits = transfer->bits_per_word;
|
||||||
|
|
||||||
|
switch (bits) {
|
||||||
|
case 8:
|
||||||
|
dws->n_bytes = 1;
|
||||||
|
dws->dma_width = 1;
|
||||||
|
dws->read = (dws->read != null_reader) ?
|
||||||
|
u8_reader : null_reader;
|
||||||
|
dws->write = (dws->write != null_writer) ?
|
||||||
|
u8_writer : null_writer;
|
||||||
|
break;
|
||||||
|
case 16:
|
||||||
|
dws->n_bytes = 2;
|
||||||
|
dws->dma_width = 2;
|
||||||
|
dws->read = (dws->read != null_reader) ?
|
||||||
|
u16_reader : null_reader;
|
||||||
|
dws->write = (dws->write != null_writer) ?
|
||||||
|
u16_writer : null_writer;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
printk(KERN_ERR "MRST SPI0: unsupported bits:"
|
||||||
|
"%db\n", bits);
|
||||||
|
message->status = -EIO;
|
||||||
|
goto early_exit;
|
||||||
|
}
|
||||||
|
|
||||||
|
cr0 = (bits - 1)
|
||||||
|
| (chip->type << SPI_FRF_OFFSET)
|
||||||
|
| (spi->mode << SPI_MODE_OFFSET)
|
||||||
|
| (chip->tmode << SPI_TMOD_OFFSET);
|
||||||
|
}
|
||||||
|
message->state = RUNNING_STATE;
|
||||||
|
|
||||||
|
/* Check if current transfer is a DMA transaction */
|
||||||
|
dws->dma_mapped = map_dma_buffers(dws);
|
||||||
|
|
||||||
|
if (!dws->dma_mapped && !chip->poll_mode) {
|
||||||
|
if (dws->rx)
|
||||||
|
imask |= SPI_INT_RXFI;
|
||||||
|
if (dws->tx)
|
||||||
|
imask |= SPI_INT_TXEI;
|
||||||
|
dws->transfer_handler = interrupt_transfer;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Reprogram registers only if
|
||||||
|
* 1. chip select changes
|
||||||
|
* 2. clk_div is changed
|
||||||
|
* 3. control value changes
|
||||||
|
*/
|
||||||
|
if (dw_readw(dws, ctrl0) != cr0 || cs_change || clk_div) {
|
||||||
|
spi_enable_chip(dws, 0);
|
||||||
|
|
||||||
|
if (dw_readw(dws, ctrl0) != cr0)
|
||||||
|
dw_writew(dws, ctrl0, cr0);
|
||||||
|
|
||||||
|
/* Set the interrupt mask, for poll mode just diable all int */
|
||||||
|
spi_mask_intr(dws, 0xff);
|
||||||
|
if (!chip->poll_mode)
|
||||||
|
spi_umask_intr(dws, imask);
|
||||||
|
|
||||||
|
spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
|
||||||
|
spi_chip_sel(dws, spi->chip_select);
|
||||||
|
spi_enable_chip(dws, 1);
|
||||||
|
|
||||||
|
if (cs_change)
|
||||||
|
dws->prev_chip = chip;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (dws->dma_mapped)
|
||||||
|
dma_transfer(dws, cs_change);
|
||||||
|
|
||||||
|
if (chip->poll_mode)
|
||||||
|
poll_transfer(dws);
|
||||||
|
|
||||||
|
return;
|
||||||
|
|
||||||
|
early_exit:
|
||||||
|
giveback(dws);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void pump_messages(struct work_struct *work)
|
||||||
|
{
|
||||||
|
struct dw_spi *dws =
|
||||||
|
container_of(work, struct dw_spi, pump_messages);
|
||||||
|
unsigned long flags;
|
||||||
|
|
||||||
|
/* Lock queue and check for queue work */
|
||||||
|
spin_lock_irqsave(&dws->lock, flags);
|
||||||
|
if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {
|
||||||
|
dws->busy = 0;
|
||||||
|
spin_unlock_irqrestore(&dws->lock, flags);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Make sure we are not already running a message */
|
||||||
|
if (dws->cur_msg) {
|
||||||
|
spin_unlock_irqrestore(&dws->lock, flags);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Extract head of queue */
|
||||||
|
dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);
|
||||||
|
list_del_init(&dws->cur_msg->queue);
|
||||||
|
|
||||||
|
/* Initial message state*/
|
||||||
|
dws->cur_msg->state = START_STATE;
|
||||||
|
dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
|
||||||
|
struct spi_transfer,
|
||||||
|
transfer_list);
|
||||||
|
dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
|
||||||
|
|
||||||
|
/* Mark as busy and launch transfers */
|
||||||
|
tasklet_schedule(&dws->pump_transfers);
|
||||||
|
|
||||||
|
dws->busy = 1;
|
||||||
|
spin_unlock_irqrestore(&dws->lock, flags);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* spi_device use this to queue in their spi_msg */
|
||||||
|
static int dw_spi_transfer(struct spi_device *spi, struct spi_message *msg)
|
||||||
|
{
|
||||||
|
struct dw_spi *dws = spi_master_get_devdata(spi->master);
|
||||||
|
unsigned long flags;
|
||||||
|
|
||||||
|
spin_lock_irqsave(&dws->lock, flags);
|
||||||
|
|
||||||
|
if (dws->run == QUEUE_STOPPED) {
|
||||||
|
spin_unlock_irqrestore(&dws->lock, flags);
|
||||||
|
return -ESHUTDOWN;
|
||||||
|
}
|
||||||
|
|
||||||
|
msg->actual_length = 0;
|
||||||
|
msg->status = -EINPROGRESS;
|
||||||
|
msg->state = START_STATE;
|
||||||
|
|
||||||
|
list_add_tail(&msg->queue, &dws->queue);
|
||||||
|
|
||||||
|
if (dws->run == QUEUE_RUNNING && !dws->busy) {
|
||||||
|
|
||||||
|
if (dws->cur_transfer || dws->cur_msg)
|
||||||
|
queue_work(dws->workqueue,
|
||||||
|
&dws->pump_messages);
|
||||||
|
else {
|
||||||
|
/* If no other data transaction in air, just go */
|
||||||
|
spin_unlock_irqrestore(&dws->lock, flags);
|
||||||
|
pump_messages(&dws->pump_messages);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
spin_unlock_irqrestore(&dws->lock, flags);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* This may be called twice for each spi dev */
|
||||||
|
static int dw_spi_setup(struct spi_device *spi)
|
||||||
|
{
|
||||||
|
struct dw_spi_chip *chip_info = NULL;
|
||||||
|
struct chip_data *chip;
|
||||||
|
|
||||||
|
if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
/* Only alloc on first setup */
|
||||||
|
chip = spi_get_ctldata(spi);
|
||||||
|
if (!chip) {
|
||||||
|
chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
|
||||||
|
if (!chip)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
chip->cs_control = null_cs_control;
|
||||||
|
chip->enable_dma = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Protocol drivers may change the chip settings, so...
|
||||||
|
* if chip_info exists, use it
|
||||||
|
*/
|
||||||
|
chip_info = spi->controller_data;
|
||||||
|
|
||||||
|
/* chip_info doesn't always exist */
|
||||||
|
if (chip_info) {
|
||||||
|
if (chip_info->cs_control)
|
||||||
|
chip->cs_control = chip_info->cs_control;
|
||||||
|
|
||||||
|
chip->poll_mode = chip_info->poll_mode;
|
||||||
|
chip->type = chip_info->type;
|
||||||
|
|
||||||
|
chip->rx_threshold = 0;
|
||||||
|
chip->tx_threshold = 0;
|
||||||
|
|
||||||
|
chip->enable_dma = chip_info->enable_dma;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (spi->bits_per_word <= 8) {
|
||||||
|
chip->n_bytes = 1;
|
||||||
|
chip->dma_width = 1;
|
||||||
|
chip->read = u8_reader;
|
||||||
|
chip->write = u8_writer;
|
||||||
|
} else if (spi->bits_per_word <= 16) {
|
||||||
|
chip->n_bytes = 2;
|
||||||
|
chip->dma_width = 2;
|
||||||
|
chip->read = u16_reader;
|
||||||
|
chip->write = u16_writer;
|
||||||
|
} else {
|
||||||
|
/* Never take >16b case for MRST SPIC */
|
||||||
|
dev_err(&spi->dev, "invalid wordsize\n");
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
chip->bits_per_word = spi->bits_per_word;
|
||||||
|
|
||||||
|
chip->speed_hz = spi->max_speed_hz;
|
||||||
|
if (chip->speed_hz)
|
||||||
|
chip->clk_div = 25000000 / chip->speed_hz;
|
||||||
|
else
|
||||||
|
chip->clk_div = 8; /* default value */
|
||||||
|
|
||||||
|
chip->tmode = 0; /* Tx & Rx */
|
||||||
|
/* Default SPI mode is SCPOL = 0, SCPH = 0 */
|
||||||
|
chip->cr0 = (chip->bits_per_word - 1)
|
||||||
|
| (chip->type << SPI_FRF_OFFSET)
|
||||||
|
| (spi->mode << SPI_MODE_OFFSET)
|
||||||
|
| (chip->tmode << SPI_TMOD_OFFSET);
|
||||||
|
|
||||||
|
spi_set_ctldata(spi, chip);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void dw_spi_cleanup(struct spi_device *spi)
|
||||||
|
{
|
||||||
|
struct chip_data *chip = spi_get_ctldata(spi);
|
||||||
|
kfree(chip);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int __init init_queue(struct dw_spi *dws)
|
||||||
|
{
|
||||||
|
INIT_LIST_HEAD(&dws->queue);
|
||||||
|
spin_lock_init(&dws->lock);
|
||||||
|
|
||||||
|
dws->run = QUEUE_STOPPED;
|
||||||
|
dws->busy = 0;
|
||||||
|
|
||||||
|
tasklet_init(&dws->pump_transfers,
|
||||||
|
pump_transfers, (unsigned long)dws);
|
||||||
|
|
||||||
|
INIT_WORK(&dws->pump_messages, pump_messages);
|
||||||
|
dws->workqueue = create_singlethread_workqueue(
|
||||||
|
dev_name(dws->master->dev.parent));
|
||||||
|
if (dws->workqueue == NULL)
|
||||||
|
return -EBUSY;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int start_queue(struct dw_spi *dws)
|
||||||
|
{
|
||||||
|
unsigned long flags;
|
||||||
|
|
||||||
|
spin_lock_irqsave(&dws->lock, flags);
|
||||||
|
|
||||||
|
if (dws->run == QUEUE_RUNNING || dws->busy) {
|
||||||
|
spin_unlock_irqrestore(&dws->lock, flags);
|
||||||
|
return -EBUSY;
|
||||||
|
}
|
||||||
|
|
||||||
|
dws->run = QUEUE_RUNNING;
|
||||||
|
dws->cur_msg = NULL;
|
||||||
|
dws->cur_transfer = NULL;
|
||||||
|
dws->cur_chip = NULL;
|
||||||
|
dws->prev_chip = NULL;
|
||||||
|
spin_unlock_irqrestore(&dws->lock, flags);
|
||||||
|
|
||||||
|
queue_work(dws->workqueue, &dws->pump_messages);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int stop_queue(struct dw_spi *dws)
|
||||||
|
{
|
||||||
|
unsigned long flags;
|
||||||
|
unsigned limit = 50;
|
||||||
|
int status = 0;
|
||||||
|
|
||||||
|
spin_lock_irqsave(&dws->lock, flags);
|
||||||
|
dws->run = QUEUE_STOPPED;
|
||||||
|
while (!list_empty(&dws->queue) && dws->busy && limit--) {
|
||||||
|
spin_unlock_irqrestore(&dws->lock, flags);
|
||||||
|
msleep(10);
|
||||||
|
spin_lock_irqsave(&dws->lock, flags);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!list_empty(&dws->queue) || dws->busy)
|
||||||
|
status = -EBUSY;
|
||||||
|
spin_unlock_irqrestore(&dws->lock, flags);
|
||||||
|
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int destroy_queue(struct dw_spi *dws)
|
||||||
|
{
|
||||||
|
int status;
|
||||||
|
|
||||||
|
status = stop_queue(dws);
|
||||||
|
if (status != 0)
|
||||||
|
return status;
|
||||||
|
destroy_workqueue(dws->workqueue);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Restart the controller, disable all interrupts, clean rx fifo */
|
||||||
|
static void spi_hw_init(struct dw_spi *dws)
|
||||||
|
{
|
||||||
|
spi_enable_chip(dws, 0);
|
||||||
|
spi_mask_intr(dws, 0xff);
|
||||||
|
spi_enable_chip(dws, 1);
|
||||||
|
flush(dws);
|
||||||
|
}
|
||||||
|
|
||||||
|
int __devinit dw_spi_add_host(struct dw_spi *dws)
|
||||||
|
{
|
||||||
|
struct spi_master *master;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
BUG_ON(dws == NULL);
|
||||||
|
|
||||||
|
master = spi_alloc_master(dws->parent_dev, 0);
|
||||||
|
if (!master) {
|
||||||
|
ret = -ENOMEM;
|
||||||
|
goto exit;
|
||||||
|
}
|
||||||
|
|
||||||
|
dws->master = master;
|
||||||
|
dws->type = SSI_MOTO_SPI;
|
||||||
|
dws->prev_chip = NULL;
|
||||||
|
dws->dma_inited = 0;
|
||||||
|
dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
|
||||||
|
|
||||||
|
ret = request_irq(dws->irq, dw_spi_irq, 0,
|
||||||
|
"dw_spi", dws);
|
||||||
|
if (ret < 0) {
|
||||||
|
dev_err(&master->dev, "can not get IRQ\n");
|
||||||
|
goto err_free_master;
|
||||||
|
}
|
||||||
|
|
||||||
|
master->mode_bits = SPI_CPOL | SPI_CPHA;
|
||||||
|
master->bus_num = dws->bus_num;
|
||||||
|
master->num_chipselect = dws->num_cs;
|
||||||
|
master->cleanup = dw_spi_cleanup;
|
||||||
|
master->setup = dw_spi_setup;
|
||||||
|
master->transfer = dw_spi_transfer;
|
||||||
|
|
||||||
|
dws->dma_inited = 0;
|
||||||
|
|
||||||
|
/* Basic HW init */
|
||||||
|
spi_hw_init(dws);
|
||||||
|
|
||||||
|
/* Initial and start queue */
|
||||||
|
ret = init_queue(dws);
|
||||||
|
if (ret) {
|
||||||
|
dev_err(&master->dev, "problem initializing queue\n");
|
||||||
|
goto err_diable_hw;
|
||||||
|
}
|
||||||
|
ret = start_queue(dws);
|
||||||
|
if (ret) {
|
||||||
|
dev_err(&master->dev, "problem starting queue\n");
|
||||||
|
goto err_diable_hw;
|
||||||
|
}
|
||||||
|
|
||||||
|
spi_master_set_devdata(master, dws);
|
||||||
|
ret = spi_register_master(master);
|
||||||
|
if (ret) {
|
||||||
|
dev_err(&master->dev, "problem registering spi master\n");
|
||||||
|
goto err_queue_alloc;
|
||||||
|
}
|
||||||
|
|
||||||
|
mrst_spi_debugfs_init(dws);
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
err_queue_alloc:
|
||||||
|
destroy_queue(dws);
|
||||||
|
err_diable_hw:
|
||||||
|
spi_enable_chip(dws, 0);
|
||||||
|
free_irq(dws->irq, dws);
|
||||||
|
err_free_master:
|
||||||
|
spi_master_put(master);
|
||||||
|
exit:
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
EXPORT_SYMBOL(dw_spi_add_host);
|
||||||
|
|
||||||
|
void __devexit dw_spi_remove_host(struct dw_spi *dws)
|
||||||
|
{
|
||||||
|
int status = 0;
|
||||||
|
|
||||||
|
if (!dws)
|
||||||
|
return;
|
||||||
|
mrst_spi_debugfs_remove(dws);
|
||||||
|
|
||||||
|
/* Remove the queue */
|
||||||
|
status = destroy_queue(dws);
|
||||||
|
if (status != 0)
|
||||||
|
dev_err(&dws->master->dev, "dw_spi_remove: workqueue will not "
|
||||||
|
"complete, message memory not freed\n");
|
||||||
|
|
||||||
|
spi_enable_chip(dws, 0);
|
||||||
|
/* Disable clk */
|
||||||
|
spi_set_clk(dws, 0);
|
||||||
|
free_irq(dws->irq, dws);
|
||||||
|
|
||||||
|
/* Disconnect from the SPI framework */
|
||||||
|
spi_unregister_master(dws->master);
|
||||||
|
}
|
||||||
|
|
||||||
|
int dw_spi_suspend_host(struct dw_spi *dws)
|
||||||
|
{
|
||||||
|
int ret = 0;
|
||||||
|
|
||||||
|
ret = stop_queue(dws);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
spi_enable_chip(dws, 0);
|
||||||
|
spi_set_clk(dws, 0);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
EXPORT_SYMBOL(dw_spi_suspend_host);
|
||||||
|
|
||||||
|
int dw_spi_resume_host(struct dw_spi *dws)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
spi_hw_init(dws);
|
||||||
|
ret = start_queue(dws);
|
||||||
|
if (ret)
|
||||||
|
dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
EXPORT_SYMBOL(dw_spi_resume_host);
|
||||||
|
|
||||||
|
MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
|
||||||
|
MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
|
||||||
|
MODULE_LICENSE("GPL v2");
|
||||||
169
drivers/spi/dw_spi_pci.c
Normal file
169
drivers/spi/dw_spi_pci.c
Normal file
|
|
@ -0,0 +1,169 @@
|
||||||
|
/*
|
||||||
|
* mrst_spi_pci.c - PCI interface driver for DW SPI Core
|
||||||
|
*
|
||||||
|
* Copyright (c) 2009, Intel Corporation.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License along
|
||||||
|
* with this program; if not, write to the Free Software Foundation,
|
||||||
|
* Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/interrupt.h>
|
||||||
|
#include <linux/pci.h>
|
||||||
|
#include <linux/spi/dw_spi.h>
|
||||||
|
#include <linux/spi/spi.h>
|
||||||
|
|
||||||
|
#define DRIVER_NAME "dw_spi_pci"
|
||||||
|
|
||||||
|
struct dw_spi_pci {
|
||||||
|
struct pci_dev *pdev;
|
||||||
|
struct dw_spi dws;
|
||||||
|
};
|
||||||
|
|
||||||
|
static int __devinit spi_pci_probe(struct pci_dev *pdev,
|
||||||
|
const struct pci_device_id *ent)
|
||||||
|
{
|
||||||
|
struct dw_spi_pci *dwpci;
|
||||||
|
struct dw_spi *dws;
|
||||||
|
int pci_bar = 0;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
printk(KERN_INFO "DW: found PCI SPI controller(ID: %04x:%04x)\n",
|
||||||
|
pdev->vendor, pdev->device);
|
||||||
|
|
||||||
|
ret = pci_enable_device(pdev);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
dwpci = kzalloc(sizeof(struct dw_spi_pci), GFP_KERNEL);
|
||||||
|
if (!dwpci) {
|
||||||
|
ret = -ENOMEM;
|
||||||
|
goto err_disable;
|
||||||
|
}
|
||||||
|
|
||||||
|
dwpci->pdev = pdev;
|
||||||
|
dws = &dwpci->dws;
|
||||||
|
|
||||||
|
/* Get basic io resource and map it */
|
||||||
|
dws->paddr = pci_resource_start(pdev, pci_bar);
|
||||||
|
dws->iolen = pci_resource_len(pdev, pci_bar);
|
||||||
|
|
||||||
|
ret = pci_request_region(pdev, pci_bar, dev_name(&pdev->dev));
|
||||||
|
if (ret)
|
||||||
|
goto err_kfree;
|
||||||
|
|
||||||
|
dws->regs = ioremap_nocache((unsigned long)dws->paddr,
|
||||||
|
pci_resource_len(pdev, pci_bar));
|
||||||
|
if (!dws->regs) {
|
||||||
|
ret = -ENOMEM;
|
||||||
|
goto err_release_reg;
|
||||||
|
}
|
||||||
|
|
||||||
|
dws->parent_dev = &pdev->dev;
|
||||||
|
dws->bus_num = 0;
|
||||||
|
dws->num_cs = 4;
|
||||||
|
dws->max_freq = 25000000; /* for Moorestwon */
|
||||||
|
dws->irq = pdev->irq;
|
||||||
|
|
||||||
|
ret = dw_spi_add_host(dws);
|
||||||
|
if (ret)
|
||||||
|
goto err_unmap;
|
||||||
|
|
||||||
|
/* PCI hook and SPI hook use the same drv data */
|
||||||
|
pci_set_drvdata(pdev, dwpci);
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
err_unmap:
|
||||||
|
iounmap(dws->regs);
|
||||||
|
err_release_reg:
|
||||||
|
pci_release_region(pdev, pci_bar);
|
||||||
|
err_kfree:
|
||||||
|
kfree(dwpci);
|
||||||
|
err_disable:
|
||||||
|
pci_disable_device(pdev);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void __devexit spi_pci_remove(struct pci_dev *pdev)
|
||||||
|
{
|
||||||
|
struct dw_spi_pci *dwpci = pci_get_drvdata(pdev);
|
||||||
|
|
||||||
|
pci_set_drvdata(pdev, NULL);
|
||||||
|
iounmap(dwpci->dws.regs);
|
||||||
|
pci_release_region(pdev, 0);
|
||||||
|
kfree(dwpci);
|
||||||
|
pci_disable_device(pdev);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef CONFIG_PM
|
||||||
|
static int spi_suspend(struct pci_dev *pdev, pm_message_t state)
|
||||||
|
{
|
||||||
|
struct dw_spi_pci *dwpci = pci_get_drvdata(pdev);
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = dw_spi_suspend_host(&dwpci->dws);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
pci_save_state(pdev);
|
||||||
|
pci_disable_device(pdev);
|
||||||
|
pci_set_power_state(pdev, pci_choose_state(pdev, state));
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int spi_resume(struct pci_dev *pdev)
|
||||||
|
{
|
||||||
|
struct dw_spi_pci *dwpci = pci_get_drvdata(pdev);
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
pci_set_power_state(pdev, PCI_D0);
|
||||||
|
pci_restore_state(pdev);
|
||||||
|
ret = pci_enable_device(pdev);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
return dw_spi_resume_host(&dwpci->dws);
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
#define spi_suspend NULL
|
||||||
|
#define spi_resume NULL
|
||||||
|
#endif
|
||||||
|
|
||||||
|
static const struct pci_device_id pci_ids[] __devinitdata = {
|
||||||
|
/* Intel Moorestown platform SPI controller 0 */
|
||||||
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0800) },
|
||||||
|
{},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct pci_driver dw_spi_driver = {
|
||||||
|
.name = DRIVER_NAME,
|
||||||
|
.id_table = pci_ids,
|
||||||
|
.probe = spi_pci_probe,
|
||||||
|
.remove = __devexit_p(spi_pci_remove),
|
||||||
|
.suspend = spi_suspend,
|
||||||
|
.resume = spi_resume,
|
||||||
|
};
|
||||||
|
|
||||||
|
static int __init mrst_spi_init(void)
|
||||||
|
{
|
||||||
|
return pci_register_driver(&dw_spi_driver);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void __exit mrst_spi_exit(void)
|
||||||
|
{
|
||||||
|
pci_unregister_driver(&dw_spi_driver);
|
||||||
|
}
|
||||||
|
|
||||||
|
module_init(mrst_spi_init);
|
||||||
|
module_exit(mrst_spi_exit);
|
||||||
|
|
||||||
|
MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
|
||||||
|
MODULE_DESCRIPTION("PCI interface driver for DW SPI Core");
|
||||||
|
MODULE_LICENSE("GPL v2");
|
||||||
|
|
@ -1294,7 +1294,7 @@ static int __init bfin_spi_probe(struct platform_device *pdev)
|
||||||
goto out_error_get_res;
|
goto out_error_get_res;
|
||||||
}
|
}
|
||||||
|
|
||||||
drv_data->regs_base = ioremap(res->start, (res->end - res->start + 1));
|
drv_data->regs_base = ioremap(res->start, resource_size(res));
|
||||||
if (drv_data->regs_base == NULL) {
|
if (drv_data->regs_base == NULL) {
|
||||||
dev_err(dev, "Cannot map IO\n");
|
dev_err(dev, "Cannot map IO\n");
|
||||||
status = -ENXIO;
|
status = -ENXIO;
|
||||||
|
|
|
||||||
|
|
@ -1013,7 +1013,7 @@ mpc8xxx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq)
|
||||||
|
|
||||||
init_completion(&mpc8xxx_spi->done);
|
init_completion(&mpc8xxx_spi->done);
|
||||||
|
|
||||||
mpc8xxx_spi->base = ioremap(mem->start, mem->end - mem->start + 1);
|
mpc8xxx_spi->base = ioremap(mem->start, resource_size(mem));
|
||||||
if (mpc8xxx_spi->base == NULL) {
|
if (mpc8xxx_spi->base == NULL) {
|
||||||
ret = -ENOMEM;
|
ret = -ENOMEM;
|
||||||
goto err_ioremap;
|
goto err_ioremap;
|
||||||
|
|
|
||||||
|
|
@ -1,7 +1,7 @@
|
||||||
/* linux/drivers/spi/spi_s3c24xx.c
|
/* linux/drivers/spi/spi_s3c24xx.c
|
||||||
*
|
*
|
||||||
* Copyright (c) 2006 Ben Dooks
|
* Copyright (c) 2006 Ben Dooks
|
||||||
* Copyright (c) 2006 Simtec Electronics
|
* Copyright 2006-2009 Simtec Electronics
|
||||||
* Ben Dooks <ben@simtec.co.uk>
|
* Ben Dooks <ben@simtec.co.uk>
|
||||||
*
|
*
|
||||||
* This program is free software; you can redistribute it and/or modify
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
|
@ -28,6 +28,11 @@
|
||||||
#include <plat/regs-spi.h>
|
#include <plat/regs-spi.h>
|
||||||
#include <mach/spi.h>
|
#include <mach/spi.h>
|
||||||
|
|
||||||
|
#include <plat/fiq.h>
|
||||||
|
#include <asm/fiq.h>
|
||||||
|
|
||||||
|
#include "spi_s3c24xx_fiq.h"
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* s3c24xx_spi_devstate - per device data
|
* s3c24xx_spi_devstate - per device data
|
||||||
* @hz: Last frequency calculated for @sppre field.
|
* @hz: Last frequency calculated for @sppre field.
|
||||||
|
|
@ -42,6 +47,13 @@ struct s3c24xx_spi_devstate {
|
||||||
u8 sppre;
|
u8 sppre;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
enum spi_fiq_mode {
|
||||||
|
FIQ_MODE_NONE = 0,
|
||||||
|
FIQ_MODE_TX = 1,
|
||||||
|
FIQ_MODE_RX = 2,
|
||||||
|
FIQ_MODE_TXRX = 3,
|
||||||
|
};
|
||||||
|
|
||||||
struct s3c24xx_spi {
|
struct s3c24xx_spi {
|
||||||
/* bitbang has to be first */
|
/* bitbang has to be first */
|
||||||
struct spi_bitbang bitbang;
|
struct spi_bitbang bitbang;
|
||||||
|
|
@ -52,6 +64,11 @@ struct s3c24xx_spi {
|
||||||
int len;
|
int len;
|
||||||
int count;
|
int count;
|
||||||
|
|
||||||
|
struct fiq_handler fiq_handler;
|
||||||
|
enum spi_fiq_mode fiq_mode;
|
||||||
|
unsigned char fiq_inuse;
|
||||||
|
unsigned char fiq_claimed;
|
||||||
|
|
||||||
void (*set_cs)(struct s3c2410_spi_info *spi,
|
void (*set_cs)(struct s3c2410_spi_info *spi,
|
||||||
int cs, int pol);
|
int cs, int pol);
|
||||||
|
|
||||||
|
|
@ -67,6 +84,7 @@ struct s3c24xx_spi {
|
||||||
struct s3c2410_spi_info *pdata;
|
struct s3c2410_spi_info *pdata;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
#define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
|
#define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
|
||||||
#define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
|
#define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
|
||||||
|
|
||||||
|
|
@ -127,7 +145,7 @@ static int s3c24xx_spi_update_state(struct spi_device *spi,
|
||||||
}
|
}
|
||||||
|
|
||||||
if (spi->mode != cs->mode) {
|
if (spi->mode != cs->mode) {
|
||||||
u8 spcon = SPCON_DEFAULT;
|
u8 spcon = SPCON_DEFAULT | S3C2410_SPCON_ENSCK;
|
||||||
|
|
||||||
if (spi->mode & SPI_CPHA)
|
if (spi->mode & SPI_CPHA)
|
||||||
spcon |= S3C2410_SPCON_CPHA_FMTB;
|
spcon |= S3C2410_SPCON_CPHA_FMTB;
|
||||||
|
|
@ -214,13 +232,196 @@ static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
|
||||||
return hw->tx ? hw->tx[count] : 0;
|
return hw->tx ? hw->tx[count] : 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#ifdef CONFIG_SPI_S3C24XX_FIQ
|
||||||
|
/* Support for FIQ based pseudo-DMA to improve the transfer speed.
|
||||||
|
*
|
||||||
|
* This code uses the assembly helper in spi_s3c24xx_spi.S which is
|
||||||
|
* used by the FIQ core to move data between main memory and the peripheral
|
||||||
|
* block. Since this is code running on the processor, there is no problem
|
||||||
|
* with cache coherency of the buffers, so we can use any buffer we like.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* struct spi_fiq_code - FIQ code and header
|
||||||
|
* @length: The length of the code fragment, excluding this header.
|
||||||
|
* @ack_offset: The offset from @data to the word to place the IRQ ACK bit at.
|
||||||
|
* @data: The code itself to install as a FIQ handler.
|
||||||
|
*/
|
||||||
|
struct spi_fiq_code {
|
||||||
|
u32 length;
|
||||||
|
u32 ack_offset;
|
||||||
|
u8 data[0];
|
||||||
|
};
|
||||||
|
|
||||||
|
extern struct spi_fiq_code s3c24xx_spi_fiq_txrx;
|
||||||
|
extern struct spi_fiq_code s3c24xx_spi_fiq_tx;
|
||||||
|
extern struct spi_fiq_code s3c24xx_spi_fiq_rx;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* ack_bit - turn IRQ into IRQ acknowledgement bit
|
||||||
|
* @irq: The interrupt number
|
||||||
|
*
|
||||||
|
* Returns the bit to write to the interrupt acknowledge register.
|
||||||
|
*/
|
||||||
|
static inline u32 ack_bit(unsigned int irq)
|
||||||
|
{
|
||||||
|
return 1 << (irq - IRQ_EINT0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* s3c24xx_spi_tryfiq - attempt to claim and setup FIQ for transfer
|
||||||
|
* @hw: The hardware state.
|
||||||
|
*
|
||||||
|
* Claim the FIQ handler (only one can be active at any one time) and
|
||||||
|
* then setup the correct transfer code for this transfer.
|
||||||
|
*
|
||||||
|
* This call updates all the necessary state information if sucessful,
|
||||||
|
* so the caller does not need to do anything more than start the transfer
|
||||||
|
* as normal, since the IRQ will have been re-routed to the FIQ handler.
|
||||||
|
*/
|
||||||
|
void s3c24xx_spi_tryfiq(struct s3c24xx_spi *hw)
|
||||||
|
{
|
||||||
|
struct pt_regs regs;
|
||||||
|
enum spi_fiq_mode mode;
|
||||||
|
struct spi_fiq_code *code;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
if (!hw->fiq_claimed) {
|
||||||
|
/* try and claim fiq if we haven't got it, and if not
|
||||||
|
* then return and simply use another transfer method */
|
||||||
|
|
||||||
|
ret = claim_fiq(&hw->fiq_handler);
|
||||||
|
if (ret)
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (hw->tx && !hw->rx)
|
||||||
|
mode = FIQ_MODE_TX;
|
||||||
|
else if (hw->rx && !hw->tx)
|
||||||
|
mode = FIQ_MODE_RX;
|
||||||
|
else
|
||||||
|
mode = FIQ_MODE_TXRX;
|
||||||
|
|
||||||
|
regs.uregs[fiq_rspi] = (long)hw->regs;
|
||||||
|
regs.uregs[fiq_rrx] = (long)hw->rx;
|
||||||
|
regs.uregs[fiq_rtx] = (long)hw->tx + 1;
|
||||||
|
regs.uregs[fiq_rcount] = hw->len - 1;
|
||||||
|
regs.uregs[fiq_rirq] = (long)S3C24XX_VA_IRQ;
|
||||||
|
|
||||||
|
set_fiq_regs(®s);
|
||||||
|
|
||||||
|
if (hw->fiq_mode != mode) {
|
||||||
|
u32 *ack_ptr;
|
||||||
|
|
||||||
|
hw->fiq_mode = mode;
|
||||||
|
|
||||||
|
switch (mode) {
|
||||||
|
case FIQ_MODE_TX:
|
||||||
|
code = &s3c24xx_spi_fiq_tx;
|
||||||
|
break;
|
||||||
|
case FIQ_MODE_RX:
|
||||||
|
code = &s3c24xx_spi_fiq_rx;
|
||||||
|
break;
|
||||||
|
case FIQ_MODE_TXRX:
|
||||||
|
code = &s3c24xx_spi_fiq_txrx;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
code = NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
BUG_ON(!code);
|
||||||
|
|
||||||
|
ack_ptr = (u32 *)&code->data[code->ack_offset];
|
||||||
|
*ack_ptr = ack_bit(hw->irq);
|
||||||
|
|
||||||
|
set_fiq_handler(&code->data, code->length);
|
||||||
|
}
|
||||||
|
|
||||||
|
s3c24xx_set_fiq(hw->irq, true);
|
||||||
|
|
||||||
|
hw->fiq_mode = mode;
|
||||||
|
hw->fiq_inuse = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* s3c24xx_spi_fiqop - FIQ core code callback
|
||||||
|
* @pw: Data registered with the handler
|
||||||
|
* @release: Whether this is a release or a return.
|
||||||
|
*
|
||||||
|
* Called by the FIQ code when another module wants to use the FIQ, so
|
||||||
|
* return whether we are currently using this or not and then update our
|
||||||
|
* internal state.
|
||||||
|
*/
|
||||||
|
static int s3c24xx_spi_fiqop(void *pw, int release)
|
||||||
|
{
|
||||||
|
struct s3c24xx_spi *hw = pw;
|
||||||
|
int ret = 0;
|
||||||
|
|
||||||
|
if (release) {
|
||||||
|
if (hw->fiq_inuse)
|
||||||
|
ret = -EBUSY;
|
||||||
|
|
||||||
|
/* note, we do not need to unroute the FIQ, as the FIQ
|
||||||
|
* vector code de-routes it to signal the end of transfer */
|
||||||
|
|
||||||
|
hw->fiq_mode = FIQ_MODE_NONE;
|
||||||
|
hw->fiq_claimed = 0;
|
||||||
|
} else {
|
||||||
|
hw->fiq_claimed = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* s3c24xx_spi_initfiq - setup the information for the FIQ core
|
||||||
|
* @hw: The hardware state.
|
||||||
|
*
|
||||||
|
* Setup the fiq_handler block to pass to the FIQ core.
|
||||||
|
*/
|
||||||
|
static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *hw)
|
||||||
|
{
|
||||||
|
hw->fiq_handler.dev_id = hw;
|
||||||
|
hw->fiq_handler.name = dev_name(hw->dev);
|
||||||
|
hw->fiq_handler.fiq_op = s3c24xx_spi_fiqop;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* s3c24xx_spi_usefiq - return if we should be using FIQ.
|
||||||
|
* @hw: The hardware state.
|
||||||
|
*
|
||||||
|
* Return true if the platform data specifies whether this channel is
|
||||||
|
* allowed to use the FIQ.
|
||||||
|
*/
|
||||||
|
static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *hw)
|
||||||
|
{
|
||||||
|
return hw->pdata->use_fiq;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* s3c24xx_spi_usingfiq - return if channel is using FIQ
|
||||||
|
* @spi: The hardware state.
|
||||||
|
*
|
||||||
|
* Return whether the channel is currently using the FIQ (separate from
|
||||||
|
* whether the FIQ is claimed).
|
||||||
|
*/
|
||||||
|
static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *spi)
|
||||||
|
{
|
||||||
|
return spi->fiq_inuse;
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
|
||||||
|
static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *s) { }
|
||||||
|
static inline void s3c24xx_spi_tryfiq(struct s3c24xx_spi *s) { }
|
||||||
|
static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *s) { return false; }
|
||||||
|
static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *s) { return false; }
|
||||||
|
|
||||||
|
#endif /* CONFIG_SPI_S3C24XX_FIQ */
|
||||||
|
|
||||||
static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
|
static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
|
||||||
{
|
{
|
||||||
struct s3c24xx_spi *hw = to_hw(spi);
|
struct s3c24xx_spi *hw = to_hw(spi);
|
||||||
|
|
||||||
dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
|
|
||||||
t->tx_buf, t->rx_buf, t->len);
|
|
||||||
|
|
||||||
hw->tx = t->tx_buf;
|
hw->tx = t->tx_buf;
|
||||||
hw->rx = t->rx_buf;
|
hw->rx = t->rx_buf;
|
||||||
hw->len = t->len;
|
hw->len = t->len;
|
||||||
|
|
@ -228,11 +429,14 @@ static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
|
||||||
|
|
||||||
init_completion(&hw->done);
|
init_completion(&hw->done);
|
||||||
|
|
||||||
|
hw->fiq_inuse = 0;
|
||||||
|
if (s3c24xx_spi_usefiq(hw) && t->len >= 3)
|
||||||
|
s3c24xx_spi_tryfiq(hw);
|
||||||
|
|
||||||
/* send the first byte */
|
/* send the first byte */
|
||||||
writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
|
writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
|
||||||
|
|
||||||
wait_for_completion(&hw->done);
|
wait_for_completion(&hw->done);
|
||||||
|
|
||||||
return hw->count;
|
return hw->count;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -254,6 +458,7 @@ static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
|
||||||
goto irq_done;
|
goto irq_done;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (!s3c24xx_spi_usingfiq(hw)) {
|
||||||
hw->count++;
|
hw->count++;
|
||||||
|
|
||||||
if (hw->rx)
|
if (hw->rx)
|
||||||
|
|
@ -265,6 +470,15 @@ static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
|
||||||
writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
|
writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
|
||||||
else
|
else
|
||||||
complete(&hw->done);
|
complete(&hw->done);
|
||||||
|
} else {
|
||||||
|
hw->count = hw->len;
|
||||||
|
hw->fiq_inuse = 0;
|
||||||
|
|
||||||
|
if (hw->rx)
|
||||||
|
hw->rx[hw->len-1] = readb(hw->regs + S3C2410_SPRDAT);
|
||||||
|
|
||||||
|
complete(&hw->done);
|
||||||
|
}
|
||||||
|
|
||||||
irq_done:
|
irq_done:
|
||||||
return IRQ_HANDLED;
|
return IRQ_HANDLED;
|
||||||
|
|
@ -322,6 +536,10 @@ static int __init s3c24xx_spi_probe(struct platform_device *pdev)
|
||||||
platform_set_drvdata(pdev, hw);
|
platform_set_drvdata(pdev, hw);
|
||||||
init_completion(&hw->done);
|
init_completion(&hw->done);
|
||||||
|
|
||||||
|
/* initialise fiq handler */
|
||||||
|
|
||||||
|
s3c24xx_spi_initfiq(hw);
|
||||||
|
|
||||||
/* setup the master state. */
|
/* setup the master state. */
|
||||||
|
|
||||||
/* the spi->mode bits understood by this driver: */
|
/* the spi->mode bits understood by this driver: */
|
||||||
|
|
|
||||||
116
drivers/spi/spi_s3c24xx_fiq.S
Normal file
116
drivers/spi/spi_s3c24xx_fiq.S
Normal file
|
|
@ -0,0 +1,116 @@
|
||||||
|
/* linux/drivers/spi/spi_s3c24xx_fiq.S
|
||||||
|
*
|
||||||
|
* Copyright 2009 Simtec Electronics
|
||||||
|
* Ben Dooks <ben@simtec.co.uk>
|
||||||
|
*
|
||||||
|
* S3C24XX SPI - FIQ pseudo-DMA transfer code
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 as
|
||||||
|
* published by the Free Software Foundation.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/linkage.h>
|
||||||
|
#include <asm/assembler.h>
|
||||||
|
|
||||||
|
#include <mach/map.h>
|
||||||
|
#include <mach/regs-irq.h>
|
||||||
|
#include <plat/regs-spi.h>
|
||||||
|
|
||||||
|
#include "spi_s3c24xx_fiq.h"
|
||||||
|
|
||||||
|
.text
|
||||||
|
|
||||||
|
@ entry to these routines is as follows, with the register names
|
||||||
|
@ defined in fiq.h so that they can be shared with the C files which
|
||||||
|
@ setup the calling registers.
|
||||||
|
@
|
||||||
|
@ fiq_rirq The base of the IRQ registers to find S3C2410_SRCPND
|
||||||
|
@ fiq_rtmp Temporary register to hold tx/rx data
|
||||||
|
@ fiq_rspi The base of the SPI register block
|
||||||
|
@ fiq_rtx The tx buffer pointer
|
||||||
|
@ fiq_rrx The rx buffer pointer
|
||||||
|
@ fiq_rcount The number of bytes to move
|
||||||
|
|
||||||
|
@ each entry starts with a word entry of how long it is
|
||||||
|
@ and an offset to the irq acknowledgment word
|
||||||
|
|
||||||
|
ENTRY(s3c24xx_spi_fiq_rx)
|
||||||
|
s3c24xx_spi_fix_rx:
|
||||||
|
.word fiq_rx_end - fiq_rx_start
|
||||||
|
.word fiq_rx_irq_ack - fiq_rx_start
|
||||||
|
fiq_rx_start:
|
||||||
|
ldr fiq_rtmp, fiq_rx_irq_ack
|
||||||
|
str fiq_rtmp, [ fiq_rirq, # S3C2410_SRCPND - S3C24XX_VA_IRQ ]
|
||||||
|
|
||||||
|
ldrb fiq_rtmp, [ fiq_rspi, # S3C2410_SPRDAT ]
|
||||||
|
strb fiq_rtmp, [ fiq_rrx ], #1
|
||||||
|
|
||||||
|
mov fiq_rtmp, #0xff
|
||||||
|
strb fiq_rtmp, [ fiq_rspi, # S3C2410_SPTDAT ]
|
||||||
|
|
||||||
|
subs fiq_rcount, fiq_rcount, #1
|
||||||
|
subnes pc, lr, #4 @@ return, still have work to do
|
||||||
|
|
||||||
|
@@ set IRQ controller so that next op will trigger IRQ
|
||||||
|
mov fiq_rtmp, #0
|
||||||
|
str fiq_rtmp, [ fiq_rirq, # S3C2410_INTMOD - S3C24XX_VA_IRQ ]
|
||||||
|
subs pc, lr, #4
|
||||||
|
|
||||||
|
fiq_rx_irq_ack:
|
||||||
|
.word 0
|
||||||
|
fiq_rx_end:
|
||||||
|
|
||||||
|
ENTRY(s3c24xx_spi_fiq_txrx)
|
||||||
|
s3c24xx_spi_fiq_txrx:
|
||||||
|
.word fiq_txrx_end - fiq_txrx_start
|
||||||
|
.word fiq_txrx_irq_ack - fiq_txrx_start
|
||||||
|
fiq_txrx_start:
|
||||||
|
|
||||||
|
ldrb fiq_rtmp, [ fiq_rspi, # S3C2410_SPRDAT ]
|
||||||
|
strb fiq_rtmp, [ fiq_rrx ], #1
|
||||||
|
|
||||||
|
ldr fiq_rtmp, fiq_txrx_irq_ack
|
||||||
|
str fiq_rtmp, [ fiq_rirq, # S3C2410_SRCPND - S3C24XX_VA_IRQ ]
|
||||||
|
|
||||||
|
ldrb fiq_rtmp, [ fiq_rtx ], #1
|
||||||
|
strb fiq_rtmp, [ fiq_rspi, # S3C2410_SPTDAT ]
|
||||||
|
|
||||||
|
subs fiq_rcount, fiq_rcount, #1
|
||||||
|
subnes pc, lr, #4 @@ return, still have work to do
|
||||||
|
|
||||||
|
mov fiq_rtmp, #0
|
||||||
|
str fiq_rtmp, [ fiq_rirq, # S3C2410_INTMOD - S3C24XX_VA_IRQ ]
|
||||||
|
subs pc, lr, #4
|
||||||
|
|
||||||
|
fiq_txrx_irq_ack:
|
||||||
|
.word 0
|
||||||
|
|
||||||
|
fiq_txrx_end:
|
||||||
|
|
||||||
|
ENTRY(s3c24xx_spi_fiq_tx)
|
||||||
|
s3c24xx_spi_fix_tx:
|
||||||
|
.word fiq_tx_end - fiq_tx_start
|
||||||
|
.word fiq_tx_irq_ack - fiq_tx_start
|
||||||
|
fiq_tx_start:
|
||||||
|
ldrb fiq_rtmp, [ fiq_rspi, # S3C2410_SPRDAT ]
|
||||||
|
|
||||||
|
ldr fiq_rtmp, fiq_tx_irq_ack
|
||||||
|
str fiq_rtmp, [ fiq_rirq, # S3C2410_SRCPND - S3C24XX_VA_IRQ ]
|
||||||
|
|
||||||
|
ldrb fiq_rtmp, [ fiq_rtx ], #1
|
||||||
|
strb fiq_rtmp, [ fiq_rspi, # S3C2410_SPTDAT ]
|
||||||
|
|
||||||
|
subs fiq_rcount, fiq_rcount, #1
|
||||||
|
subnes pc, lr, #4 @@ return, still have work to do
|
||||||
|
|
||||||
|
mov fiq_rtmp, #0
|
||||||
|
str fiq_rtmp, [ fiq_rirq, # S3C2410_INTMOD - S3C24XX_VA_IRQ ]
|
||||||
|
subs pc, lr, #4
|
||||||
|
|
||||||
|
fiq_tx_irq_ack:
|
||||||
|
.word 0
|
||||||
|
|
||||||
|
fiq_tx_end:
|
||||||
|
|
||||||
|
.end
|
||||||
26
drivers/spi/spi_s3c24xx_fiq.h
Normal file
26
drivers/spi/spi_s3c24xx_fiq.h
Normal file
|
|
@ -0,0 +1,26 @@
|
||||||
|
/* linux/drivers/spi/spi_s3c24xx_fiq.h
|
||||||
|
*
|
||||||
|
* Copyright 2009 Simtec Electronics
|
||||||
|
* Ben Dooks <ben@simtec.co.uk>
|
||||||
|
*
|
||||||
|
* S3C24XX SPI - FIQ pseudo-DMA transfer support
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 as
|
||||||
|
* published by the Free Software Foundation.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* We have R8 through R13 to play with */
|
||||||
|
|
||||||
|
#ifdef __ASSEMBLY__
|
||||||
|
#define __REG_NR(x) r##x
|
||||||
|
#else
|
||||||
|
#define __REG_NR(x) (x)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define fiq_rspi __REG_NR(8)
|
||||||
|
#define fiq_rtmp __REG_NR(9)
|
||||||
|
#define fiq_rrx __REG_NR(10)
|
||||||
|
#define fiq_rtx __REG_NR(11)
|
||||||
|
#define fiq_rcount __REG_NR(12)
|
||||||
|
#define fiq_rirq __REG_NR(13)
|
||||||
1196
drivers/spi/spi_s3c64xx.c
Normal file
1196
drivers/spi/spi_s3c64xx.c
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -148,7 +148,7 @@ static int sh_sci_spi_probe(struct platform_device *dev)
|
||||||
ret = -ENOENT;
|
ret = -ENOENT;
|
||||||
goto err1;
|
goto err1;
|
||||||
}
|
}
|
||||||
sp->membase = ioremap(r->start, r->end - r->start + 1);
|
sp->membase = ioremap(r->start, resource_size(r));
|
||||||
if (!sp->membase) {
|
if (!sp->membase) {
|
||||||
ret = -ENXIO;
|
ret = -ENXIO;
|
||||||
goto err1;
|
goto err1;
|
||||||
|
|
|
||||||
|
|
@ -375,12 +375,10 @@ static int __init txx9spi_probe(struct platform_device *dev)
|
||||||
res = platform_get_resource(dev, IORESOURCE_MEM, 0);
|
res = platform_get_resource(dev, IORESOURCE_MEM, 0);
|
||||||
if (!res)
|
if (!res)
|
||||||
goto exit_busy;
|
goto exit_busy;
|
||||||
if (!devm_request_mem_region(&dev->dev,
|
if (!devm_request_mem_region(&dev->dev, res->start, resource_size(res),
|
||||||
res->start, res->end - res->start + 1,
|
|
||||||
"spi_txx9"))
|
"spi_txx9"))
|
||||||
goto exit_busy;
|
goto exit_busy;
|
||||||
c->membase = devm_ioremap(&dev->dev,
|
c->membase = devm_ioremap(&dev->dev, res->start, resource_size(res));
|
||||||
res->start, res->end - res->start + 1);
|
|
||||||
if (!c->membase)
|
if (!c->membase)
|
||||||
goto exit_busy;
|
goto exit_busy;
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -53,7 +53,7 @@
|
||||||
#define SPIDEV_MAJOR 153 /* assigned */
|
#define SPIDEV_MAJOR 153 /* assigned */
|
||||||
#define N_SPI_MINORS 32 /* ... up to 256 */
|
#define N_SPI_MINORS 32 /* ... up to 256 */
|
||||||
|
|
||||||
static unsigned long minors[N_SPI_MINORS / BITS_PER_LONG];
|
static DECLARE_BITMAP(minors, N_SPI_MINORS);
|
||||||
|
|
||||||
|
|
||||||
/* Bit masks for spi_device.mode management. Note that incorrect
|
/* Bit masks for spi_device.mode management. Note that incorrect
|
||||||
|
|
@ -558,7 +558,7 @@ static struct class *spidev_class;
|
||||||
|
|
||||||
/*-------------------------------------------------------------------------*/
|
/*-------------------------------------------------------------------------*/
|
||||||
|
|
||||||
static int spidev_probe(struct spi_device *spi)
|
static int __devinit spidev_probe(struct spi_device *spi)
|
||||||
{
|
{
|
||||||
struct spidev_data *spidev;
|
struct spidev_data *spidev;
|
||||||
int status;
|
int status;
|
||||||
|
|
@ -607,7 +607,7 @@ static int spidev_probe(struct spi_device *spi)
|
||||||
return status;
|
return status;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int spidev_remove(struct spi_device *spi)
|
static int __devexit spidev_remove(struct spi_device *spi)
|
||||||
{
|
{
|
||||||
struct spidev_data *spidev = spi_get_drvdata(spi);
|
struct spidev_data *spidev = spi_get_drvdata(spi);
|
||||||
|
|
||||||
|
|
@ -629,7 +629,7 @@ static int spidev_remove(struct spi_device *spi)
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct spi_driver spidev_spi = {
|
static struct spi_driver spidev_spi_driver = {
|
||||||
.driver = {
|
.driver = {
|
||||||
.name = "spidev",
|
.name = "spidev",
|
||||||
.owner = THIS_MODULE,
|
.owner = THIS_MODULE,
|
||||||
|
|
@ -661,14 +661,14 @@ static int __init spidev_init(void)
|
||||||
|
|
||||||
spidev_class = class_create(THIS_MODULE, "spidev");
|
spidev_class = class_create(THIS_MODULE, "spidev");
|
||||||
if (IS_ERR(spidev_class)) {
|
if (IS_ERR(spidev_class)) {
|
||||||
unregister_chrdev(SPIDEV_MAJOR, spidev_spi.driver.name);
|
unregister_chrdev(SPIDEV_MAJOR, spidev_spi_driver.driver.name);
|
||||||
return PTR_ERR(spidev_class);
|
return PTR_ERR(spidev_class);
|
||||||
}
|
}
|
||||||
|
|
||||||
status = spi_register_driver(&spidev_spi);
|
status = spi_register_driver(&spidev_spi_driver);
|
||||||
if (status < 0) {
|
if (status < 0) {
|
||||||
class_destroy(spidev_class);
|
class_destroy(spidev_class);
|
||||||
unregister_chrdev(SPIDEV_MAJOR, spidev_spi.driver.name);
|
unregister_chrdev(SPIDEV_MAJOR, spidev_spi_driver.driver.name);
|
||||||
}
|
}
|
||||||
return status;
|
return status;
|
||||||
}
|
}
|
||||||
|
|
@ -676,9 +676,9 @@ module_init(spidev_init);
|
||||||
|
|
||||||
static void __exit spidev_exit(void)
|
static void __exit spidev_exit(void)
|
||||||
{
|
{
|
||||||
spi_unregister_driver(&spidev_spi);
|
spi_unregister_driver(&spidev_spi_driver);
|
||||||
class_destroy(spidev_class);
|
class_destroy(spidev_class);
|
||||||
unregister_chrdev(SPIDEV_MAJOR, spidev_spi.driver.name);
|
unregister_chrdev(SPIDEV_MAJOR, spidev_spi_driver.driver.name);
|
||||||
}
|
}
|
||||||
module_exit(spidev_exit);
|
module_exit(spidev_exit);
|
||||||
|
|
||||||
|
|
|
||||||
212
include/linux/spi/dw_spi.h
Normal file
212
include/linux/spi/dw_spi.h
Normal file
|
|
@ -0,0 +1,212 @@
|
||||||
|
#ifndef DW_SPI_HEADER_H
|
||||||
|
#define DW_SPI_HEADER_H
|
||||||
|
#include <linux/io.h>
|
||||||
|
|
||||||
|
/* Bit fields in CTRLR0 */
|
||||||
|
#define SPI_DFS_OFFSET 0
|
||||||
|
|
||||||
|
#define SPI_FRF_OFFSET 4
|
||||||
|
#define SPI_FRF_SPI 0x0
|
||||||
|
#define SPI_FRF_SSP 0x1
|
||||||
|
#define SPI_FRF_MICROWIRE 0x2
|
||||||
|
#define SPI_FRF_RESV 0x3
|
||||||
|
|
||||||
|
#define SPI_MODE_OFFSET 6
|
||||||
|
#define SPI_SCPH_OFFSET 6
|
||||||
|
#define SPI_SCOL_OFFSET 7
|
||||||
|
#define SPI_TMOD_OFFSET 8
|
||||||
|
#define SPI_TMOD_TR 0x0 /* xmit & recv */
|
||||||
|
#define SPI_TMOD_TO 0x1 /* xmit only */
|
||||||
|
#define SPI_TMOD_RO 0x2 /* recv only */
|
||||||
|
#define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
|
||||||
|
|
||||||
|
#define SPI_SLVOE_OFFSET 10
|
||||||
|
#define SPI_SRL_OFFSET 11
|
||||||
|
#define SPI_CFS_OFFSET 12
|
||||||
|
|
||||||
|
/* Bit fields in SR, 7 bits */
|
||||||
|
#define SR_MASK 0x7f /* cover 7 bits */
|
||||||
|
#define SR_BUSY (1 << 0)
|
||||||
|
#define SR_TF_NOT_FULL (1 << 1)
|
||||||
|
#define SR_TF_EMPT (1 << 2)
|
||||||
|
#define SR_RF_NOT_EMPT (1 << 3)
|
||||||
|
#define SR_RF_FULL (1 << 4)
|
||||||
|
#define SR_TX_ERR (1 << 5)
|
||||||
|
#define SR_DCOL (1 << 6)
|
||||||
|
|
||||||
|
/* Bit fields in ISR, IMR, RISR, 7 bits */
|
||||||
|
#define SPI_INT_TXEI (1 << 0)
|
||||||
|
#define SPI_INT_TXOI (1 << 1)
|
||||||
|
#define SPI_INT_RXUI (1 << 2)
|
||||||
|
#define SPI_INT_RXOI (1 << 3)
|
||||||
|
#define SPI_INT_RXFI (1 << 4)
|
||||||
|
#define SPI_INT_MSTI (1 << 5)
|
||||||
|
|
||||||
|
/* TX RX interrupt level threshhold, max can be 256 */
|
||||||
|
#define SPI_INT_THRESHOLD 32
|
||||||
|
|
||||||
|
enum dw_ssi_type {
|
||||||
|
SSI_MOTO_SPI = 0,
|
||||||
|
SSI_TI_SSP,
|
||||||
|
SSI_NS_MICROWIRE,
|
||||||
|
};
|
||||||
|
|
||||||
|
struct dw_spi_reg {
|
||||||
|
u32 ctrl0;
|
||||||
|
u32 ctrl1;
|
||||||
|
u32 ssienr;
|
||||||
|
u32 mwcr;
|
||||||
|
u32 ser;
|
||||||
|
u32 baudr;
|
||||||
|
u32 txfltr;
|
||||||
|
u32 rxfltr;
|
||||||
|
u32 txflr;
|
||||||
|
u32 rxflr;
|
||||||
|
u32 sr;
|
||||||
|
u32 imr;
|
||||||
|
u32 isr;
|
||||||
|
u32 risr;
|
||||||
|
u32 txoicr;
|
||||||
|
u32 rxoicr;
|
||||||
|
u32 rxuicr;
|
||||||
|
u32 msticr;
|
||||||
|
u32 icr;
|
||||||
|
u32 dmacr;
|
||||||
|
u32 dmatdlr;
|
||||||
|
u32 dmardlr;
|
||||||
|
u32 idr;
|
||||||
|
u32 version;
|
||||||
|
u32 dr; /* Currently oper as 32 bits,
|
||||||
|
though only low 16 bits matters */
|
||||||
|
} __packed;
|
||||||
|
|
||||||
|
struct dw_spi {
|
||||||
|
struct spi_master *master;
|
||||||
|
struct spi_device *cur_dev;
|
||||||
|
struct device *parent_dev;
|
||||||
|
enum dw_ssi_type type;
|
||||||
|
|
||||||
|
void __iomem *regs;
|
||||||
|
unsigned long paddr;
|
||||||
|
u32 iolen;
|
||||||
|
int irq;
|
||||||
|
u32 max_freq; /* max bus freq supported */
|
||||||
|
|
||||||
|
u16 bus_num;
|
||||||
|
u16 num_cs; /* supported slave numbers */
|
||||||
|
|
||||||
|
/* Driver message queue */
|
||||||
|
struct workqueue_struct *workqueue;
|
||||||
|
struct work_struct pump_messages;
|
||||||
|
spinlock_t lock;
|
||||||
|
struct list_head queue;
|
||||||
|
int busy;
|
||||||
|
int run;
|
||||||
|
|
||||||
|
/* Message Transfer pump */
|
||||||
|
struct tasklet_struct pump_transfers;
|
||||||
|
|
||||||
|
/* Current message transfer state info */
|
||||||
|
struct spi_message *cur_msg;
|
||||||
|
struct spi_transfer *cur_transfer;
|
||||||
|
struct chip_data *cur_chip;
|
||||||
|
struct chip_data *prev_chip;
|
||||||
|
size_t len;
|
||||||
|
void *tx;
|
||||||
|
void *tx_end;
|
||||||
|
void *rx;
|
||||||
|
void *rx_end;
|
||||||
|
int dma_mapped;
|
||||||
|
dma_addr_t rx_dma;
|
||||||
|
dma_addr_t tx_dma;
|
||||||
|
size_t rx_map_len;
|
||||||
|
size_t tx_map_len;
|
||||||
|
u8 n_bytes; /* current is a 1/2 bytes op */
|
||||||
|
u8 max_bits_per_word; /* maxim is 16b */
|
||||||
|
u32 dma_width;
|
||||||
|
int cs_change;
|
||||||
|
int (*write)(struct dw_spi *dws);
|
||||||
|
int (*read)(struct dw_spi *dws);
|
||||||
|
irqreturn_t (*transfer_handler)(struct dw_spi *dws);
|
||||||
|
void (*cs_control)(u32 command);
|
||||||
|
|
||||||
|
/* Dma info */
|
||||||
|
int dma_inited;
|
||||||
|
struct dma_chan *txchan;
|
||||||
|
struct dma_chan *rxchan;
|
||||||
|
int txdma_done;
|
||||||
|
int rxdma_done;
|
||||||
|
u64 tx_param;
|
||||||
|
u64 rx_param;
|
||||||
|
struct device *dma_dev;
|
||||||
|
dma_addr_t dma_addr;
|
||||||
|
|
||||||
|
/* Bus interface info */
|
||||||
|
void *priv;
|
||||||
|
#ifdef CONFIG_DEBUG_FS
|
||||||
|
struct dentry *debugfs;
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
|
||||||
|
#define dw_readl(dw, name) \
|
||||||
|
__raw_readl(&(((struct dw_spi_reg *)dw->regs)->name))
|
||||||
|
#define dw_writel(dw, name, val) \
|
||||||
|
__raw_writel((val), &(((struct dw_spi_reg *)dw->regs)->name))
|
||||||
|
#define dw_readw(dw, name) \
|
||||||
|
__raw_readw(&(((struct dw_spi_reg *)dw->regs)->name))
|
||||||
|
#define dw_writew(dw, name, val) \
|
||||||
|
__raw_writew((val), &(((struct dw_spi_reg *)dw->regs)->name))
|
||||||
|
|
||||||
|
static inline void spi_enable_chip(struct dw_spi *dws, int enable)
|
||||||
|
{
|
||||||
|
dw_writel(dws, ssienr, (enable ? 1 : 0));
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void spi_set_clk(struct dw_spi *dws, u16 div)
|
||||||
|
{
|
||||||
|
dw_writel(dws, baudr, div);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void spi_chip_sel(struct dw_spi *dws, u16 cs)
|
||||||
|
{
|
||||||
|
if (cs > dws->num_cs)
|
||||||
|
return;
|
||||||
|
dw_writel(dws, ser, 1 << cs);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Disable IRQ bits */
|
||||||
|
static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
|
||||||
|
{
|
||||||
|
u32 new_mask;
|
||||||
|
|
||||||
|
new_mask = dw_readl(dws, imr) & ~mask;
|
||||||
|
dw_writel(dws, imr, new_mask);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Enable IRQ bits */
|
||||||
|
static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
|
||||||
|
{
|
||||||
|
u32 new_mask;
|
||||||
|
|
||||||
|
new_mask = dw_readl(dws, imr) | mask;
|
||||||
|
dw_writel(dws, imr, new_mask);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Each SPI slave device to work with dw_api controller should
|
||||||
|
* has such a structure claiming its working mode (PIO/DMA etc),
|
||||||
|
* which can be save in the "controller_data" member of the
|
||||||
|
* struct spi_device
|
||||||
|
*/
|
||||||
|
struct dw_spi_chip {
|
||||||
|
u8 poll_mode; /* 0 for contoller polling mode */
|
||||||
|
u8 type; /* SPI/SSP/Micrwire */
|
||||||
|
u8 enable_dma;
|
||||||
|
void (*cs_control)(u32 command);
|
||||||
|
};
|
||||||
|
|
||||||
|
extern int dw_spi_add_host(struct dw_spi *dws);
|
||||||
|
extern void dw_spi_remove_host(struct dw_spi *dws);
|
||||||
|
extern int dw_spi_suspend_host(struct dw_spi *dws);
|
||||||
|
extern int dw_spi_resume_host(struct dw_spi *dws);
|
||||||
|
#endif /* DW_SPI_HEADER_H */
|
||||||
Loading…
Reference in a new issue